FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5950 Discussions

Design using Altera Vip suite

Altera_Forum
Honored Contributor II
842 Views

Hi , 

 

I am using VIP suite to create a simple design with DVI input and converting the parallel plane dvi to sequential plane and do 2d filtering on it and display on the output. 

 

Can anyone help me with these critical warnings? 

 

 

Critical Warning: PLL "video_pll:inst1|altpll:altpll_component|altpll_l0c2:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_A14" 

 

Critical Warning: (Critical) Rule A101: Design should not contain combinational loops. Found 1 combinational loop(s) related to this rule. 

Critical Warning: Node "scop_top:inst|vga_in_inst:the_vga_in_inst|alt_vipcti101_Vid2IS:vga_in_inst|avalon_st_output.packet_post_swap~0" 

 

Critical Warning: (High) Rule R101: Combinational logic used as a reset signal should be synchronized. Found 1 node(s) related to this rule. 

Critical Warning: Node "scop_top:inst|alt_vip_scl_0:the_alt_vip_scl_0|alt_vip_scl_0_GN:auto_inst|r01038uv1mgcqkxzh2i4cwr9q8h49tn~0"
0 Kudos
0 Replies
Reply