FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Display Port IP video input format

User1580469001956815
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May I ask if the Hsync and Vsync of the display port ip input have video interface signal drift, because I have a 4k video source, the number of hsync lines per frame may be 2222 or 2221, but there is no way for such images Drive the panel, but my own production of VESA standard 4k video image works normally. I want to confirm if the display port can accept hsync more than 1-2 cycles or occasionally less hsync images.

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BoonT_Intel
Moderator
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Hi Sir,

Unfortunately the DP IP core only able to Accepts standard H-sync/V-sync input signal.

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