Documentation for Cyclone 10 GX core components?

[LGonz14]

Using the mega-function wizard, I'm generating a GPIO IP in DDIO register mode. The mega-function wizard generated several files, among them altera_gpio.sv was found. Within this module, an instance of cyclone10gx_ddio_in gets generated when data direction is set to input. During compilation, I'm getting the following never seen error:

Error(17044): Illegal connection on I/O input buffer primitive u31dc_0|u31pipe_0|u31ddiorx|gpio_0|core|gpio_one_bit.i_loop[23].altera_gpio_bit_i|input_buffer.ibuf. Source I/O pin u31dc_0|u31pipe_0|pipe_rx_phy[23] drives out to destinations other than the specified I/O input buffer primitive. Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.

Does anyone know where I can get additional documentation with regards to the cyclone10gx_ddio_in core component?

Thank you!

Luis

[Kenny_Tan]

Hi Luis,

You can refer to here https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf

What IO standard that you were using for the GPIO pin?

[LGonz14]

​Thank you!

Unfortunately, that document doesn't provide me with additional information regarding the cyclone10gx_ddio_in module being instantiated within the altera_gpio_one_bit module. The GPIO when instantiated, interfaces with an altera PHY transceiver instance on the following logical port pins:

pipe_phy_status

pipe_rx_status

pipe_rx_valid

rx_data

rx_datak

Here is a code snipped showing the actual connections:

wire [23:0] pipe_rx_phy = {1'b0,

                                                  pipe_phy_status,   // 1 bit

                                                  pipe_rx_status,      // 3 bits

                                                  pipe_rx_valid,        // 1 bit

                                                  rx_datak,                 // 2 bits

                                                  rx_data                    // 16 bits

                                                  } /* synthesis keep */;

wire [23:0] pipe_rx_h;

wire [23:0] pipe_rx_l;

// Instantiate GPIO in DDIO register mode

mf_ddio_rx ddio_rx (

  .datain (pipe_rx_phy),

  .clk (local_clk),

  .dataout_h (pipe_rx_h),

  .dataout_l (pipe_rx_l)

);

where can I find additional information about the cyclone10gx_ddio_in module?

Regards,

Luis

[YuanLi_S_Intel]

Hi Luis,

Error(17044): Illegal connection on I/O input buffer primitive u31dc_0|u31pipe_0|u31ddiorx|gpio_0|core|gpio_one_bit.i_loop[23].altera_gpio_bit_i|input_buffer.ibuf. Source I/O pin u31dc_0|u31pipe_0|pipe_rx_phy[23] drives out to destinations other than the specified I/O input buffer primitive. Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.

This error message indicates that the IP's input pin is connected to somewhere else instead of buffer. Can you check your design?

Thank You

[LGonz14]

​Please read my previous post. I specified where the input pin is connected to.. the GPIO instance in register DDIO mode is interfacing with a PHY transceiver instance..

Thank you!

Luis

[YuanLi_S_Intel]

Hi Luis,

I have tried to duplicate the issue but unfortunately i am not able to do so. May i know which quartus version you are using? Also, the setting is important.

Thank You.

[LGonz14]

​Hi,

I'm using Quartus Prime Pro version 17.1.2 build 304. Which settings are you referring to, the quartus settings or the GPIO ip settings?

[YuanLi_S_Intel]

Hi Luis,

Yes, i am referring to the setting of GPIO IP. Can you share me your complete setting? or the design?

Thank You

[LGonz14]

​The GPIO IP settings for the mf_ddio_rx ddio_rx is as follows. Please see attachment..  

Thank you!

[YuanLi_S_Intel]

Hi Luis,

Please allow me to clarify. So you are connecting the PHY transceiver instance IP to this GPIO IP in FPGA?

If it so, it cannot be. This IP is meant for connecting with input/output from external devices.

Thank You.