Assume I have a component which includes something like the following lines:
bool input_0; bool input_1; bool input_2; bool input_3; bool wire_0; bool wire_1; bool output_0; wire_0 = input_0 & input_1; wire_1 = wire_0 & input_2; ouput_0 = wire_1 & input_3;
The above code is effectively computing a four-input AND operation which is broken down to three two-input AND operations.
If the above code was written in Verilog, it would have been mapped to a single ALUT which takes all four inputs and calculates the output at one shot.
I was wondering if the same would happen if I ran the HLS Compiler flow. In other words, If I pass the above code to HLS and later to Quartus, does it allocate registers to wire_0 and wire_1 and compute them separately before generating the final output or will merge these into a four-input AND operation.
May I know that do you have insert the "component" keyword in the source code before the top-level C++ function to be synthesized as mentioned in Chapter 3: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls.pdf
If yes, can I have the .cpp code file for further investigation?