I have created the example design for Interlaken Gen2 for Stratix 10. The example design instantiates three ATX PLL, the ceter one is used as the transmit PLL while the top and bottom ones are used as Clock Buffers. I noticed that the pll_refclk0 input of the ATX PLLs being used as a clock buffer is tied to 0 and is powered down. Is that the correct way to implement an ATX PLL as a buffer?
I am not familiar with Interlaken GEN 2 design implementation but below is the ground rule of refclk connection of the ATX_PLL that act as clock buffer
I believe the reference design operate using option 2. That's why you see clock buffer ATX_PLL refclk pin is tied to GND.