The sampling clock is the device clock or reference clock to the FPGA Tx PLL and RX CDR. The transceiver FPGA PLL has a PPM limit of +/-100 PPM for JESD IP. If the variation is within this PPM tolerance, the JESD204 IP core can work with it. However, 5-10% is more than +/- 100PPM. Hence, it will not work for FPGA JESD 204B IP Core. The only way to make this work is to use another external clock controller chip to maintain the PPM before feeding it to the FPGA.