We have a use case where we wanted to use the Descriptor controller of A10 AVMM DMA with pipelined accesses on Write DMA Avalon-MM Master port. Actually we need a huge delay to respond with the data for read accceses from wr_dma interface. So we wanted to pipeline the read addresses from the DMA descriptor controller Write DMA Avalon-MM Master port to optimize the read performance. The AVMM DMA userguide for A10 does not talk about this. Can you please confirm if the above usage is feasible with AVMM DMA or not.
If you are using the internal descriptor controller of AVMM DMA PCIe IP, I don’t see there is an option to control the delay of descriptor controller, therefore, I afraid that this is not feasible to do this by using the internal descriptor controller.
I'm sorry for the confusion. The delay is required for the read-transactions from Read data mover to application, where data is moved from application to the system memory. We do not need any delay for the descriptor controller transaction as these are always Descriptor table writes. We don't have any specific requirement for Descriptor controller instance.
Please clarify if pipe-lining is possible for read requests from PCIe Read DMA Data Move of AVMM DMA.