Community
cancel
Showing results for 
Search instead for 
Did you mean: 
RamaMohan
Novice
2,479 Views

Does wr_dma interface of AVMM DMA descriptor controller support pipelined reads from application interface in A10

Hi,

We have a use case where we wanted to use the Descriptor controller of A10 AVMM DMA with pipelined accesses on Write DMA Avalon-MM Master port. Actually we need a huge delay to respond with the data for read accceses from wr_dma interface. So we wanted to pipeline the read addresses from the DMA descriptor controller Write DMA Avalon-MM Master port to optimize the read performance. The AVMM DMA userguide for A10 does not talk about this. Can you please confirm if the above usage is feasible with AVMM DMA or not.

 

Thanks,

RamaMohan

0 Kudos
6 Replies
GuaBin_N_Intel
Employee
40 Views

There are few different DMA IPs in the Platform designer. Are you referring to this PCIE specific https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm_dma.pdf?

RamaMohan
Novice
40 Views

Yes, I'm referring specifically to the the PCIe AVMM DMA pointed by you(Arria10). We are using version 17.1 of the Platform Designer.

 

Thanks,

RamaMohan

GuaBin_N_Intel
Employee
40 Views

If you are using the internal descriptor controller of AVMM DMA PCIe IP, I don’t see there is an option to control the delay of descriptor controller, therefore, I afraid that this is not feasible to do this by using the internal descriptor controller.

RamaMohan
Novice
40 Views

Hi GNg,

I'm sorry for the confusion. The delay is required for the read-transactions from Read data mover to application, where data is moved from application to the system memory. We do not need any delay for the descriptor controller transaction as these are always Descriptor table writes. We don't have any specific requirement for Descriptor controller instance.

Please clarify if pipe-lining is possible for read requests from PCIe Read DMA Data Move of AVMM DMA.

 

Thanks,

RamaMohan

GuaBin_N_Intel
Employee
40 Views

 I afraid that the pipe-lining is not an option as well from Read DMA mover

RamaMohan
Novice
40 Views

Hi GNg,

Thanks for the clarification. Will let you know if I have any further questions.

 

Regards,

Ramamohan