FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

FFT v6.1 - sink_ready de-asserting by itself

Long word length support in DSP Builder 7.1

Microtronix HyperDrive Multi-port DDR2 Memory Controller IP

Differences between Atlantic and Avalon Streaming Protocols

Clock enable bug with FIR compiler v3.3.1 and v6.1

VGA 24 bit Avalon???

DDR interface that spans multiple sides of the device

DDR II SRAM (not SDRAM) interface to Stratix II

FFT - block floating point scaling (AN 404)

What USB Phy would bolt up to a CAST CUSB core?

PAL-to-NTSC Conversion IP

Does Altera support ZBT SRAM for Stratix II devices?

Does Altera have USB 2.0 host core?

ALT2GXB: Disableing 8b10b in basic mode

DSP Builder with open source Simulink alternative

Featured Content

How to use CXL IP Design Example on DK-DEV-AGI027RBES

Avalon-MM to PCIe address translation table settings

Quartus MSGDMA core when used between Memory Mapped and Avalon ST transfers