FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

question for IP core creating

Exporting DSP Builder Modules to HDL Designs

Phy Input Clock DP83848C PHYTER

DDR local_wdata to mem_dq incorrect outpu

the problem of programming the PCIe pex_exmaple_design

Audio core from Terasic vs Altera UP

Anyone using Altera PCIe core with Avalon-MM in SOPC?

CRC Compiler Settings

Is the pin assignment changing right?

Use CRU of SIIGX as reference clock for ALTLVDS

when i tried to import the hdl file to simulink, i got the following error message

Dual port signal import into the Matlab

Megawizard pins do not match datasheets

PCI Express & switch boards

DSP Builder installation Problem

Featured Content

Tone Mapping Operator IP Malfunctioning

Unable to simulate DDR3 controller

AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)