when i tried to import the hdl file to simulink, i got the following error message

[Altera_Forum]

Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings 

Info: Peak virtual memory: 159 megabytes  Info: Processing ended: Sat Apr 25 19:55:03 2009  Info: Elapsed time: 00:00:02  Info: Total CPU time (on all processors): 00:00:01   Quartus II Analysis & Synthesis was successful    But a error box pops up and says " Invalid Mex-file 'e:\soft\quartus\quartus\dsp_builder\bin\al_dspbuilder_mAltr_Pvolp.dll' Can not find the specified module"?   what does this mean?  thanks.

[Altera_Forum]

It means that it can't find the dependencies for alt_dpsbuilder_mAltr_PvoIp.dll. This would usually mean that you were missing files on your computer or your installation was incomplete. 

 What version of DSP Builder are you using? What version of Windows are you using?  Another thing to try is download "depends" from http://www.dependencywalker.com/ (http://www.dependencywalker.com/). Then run it on the DLL in e:\soft\quartus\quartus\dsp_builder\bin. That should tell you what you are missing.

[Altera_Forum]

thanks. 

the version of DSP Builder is 8.1 and the version of matlab is 2008a. Windows XP. I copied the missing files "libmex.dll libmx.dll dwmapi.dll" to the directory "..\dsp_builder\bin" and complied the module again. This time, the message box said " Error generating simulation model." DSP Builder Fatal Error: uart: Unable to resolve name 'wrn' as a wire or I/O

[Altera_Forum]

Does simulation/generation without HDL Import blocks work? 

 And is it a 32-bit version of MATLAB?

[Altera_Forum]

It is a 32-bit version of Matlab.

[Altera_Forum]

You've only answer half my questions... do you only want half a solution?

[Altera_Forum]

sorry. The simulation without HDL import blocks works well. 

I copied the missing files "libmex.dll libmx.dll dwmapi.dll" to the directory "..\dsp_builder\bin" and complied the module again. This time, the message box said " Error generating simulation model. DSP Builder Fatal Error: uart: Unable to resolve name 'wrn' as a wire or I/O" Is there anything wrong with the verilog source code? I download the code from website and it can be synthetized successfully in Quartus II.

[Altera_Forum]

Hmmm, you shouldn't have to copy those files into that directory. They should be picked up automatically. Certainly I've never needed to do that. On the other hand, if it works... 

 Have you tried upgrading to DSPB and Quartus 9.0?  One possibility is you have an interaction between different versions of DSPB and Quartus. Do you have more than one version installed? If so make sure that QUARTUS_VERSION and any paths in PATH point to the right versions. Also please delete the DSPBuilder_<mode>_import directory and try regenerating.  If all else fails you could try posting a cut down model that fails along with verilog source code and I can try to replicate.

[Altera_Forum]

I was having the problem with the "Unable to resolve name XXX as a wire or I/O". I tried a few things but here's the one that seems to have worked. The signal it was complaining about was the clock half of an input data/clock serial stream. It ran into a dual-clock fifo that synchronized the data with the main system clock. The same clock also ran into a module that estimated the input data rate by counting edges of this clock using the main system clock. In short, it was used as both a clock and non-clock signal.  

 Adding some logic up front so that the signal was not used as a clock made the error go away. Sorry for the rough description. I can elaborate if necessary.