I have made a ALT2GXB Tansceiver design with a StratixIIGX using basic double width mode. I'm getting data from the ALT2GXB Receiver. The clock recovery unit of the receiver section is recovering the clock from the data. Now i wanna use this clock as a reference clock for a ALTLVDS SERDES Block. But this seems not to be allowed. I think that is because bad jitter performance of the high speed I/O's. The only way i can think of doing such a design is routing the rx_outclock of the ALT2GXB Block to a clock output pin, maybe thru a clock conditioner and back again. But i am pretty sure, that i am overlooking something here and that this design will have bad jitter performance.
Currently, the design runs fine in a external optical fiber loopback setup on a PCIE Devkit as long as i "steal" the reference clock from the Transmitter portion of the design, because thats the only 0ppm clock besides the rx outclock on the receiver side.
I have read the docs up and down but can only see that the reference clock for the High Speed IO'a must come from dedicated refclock pins or a PLL. It would be very thankful for any help.
