Driving multiple DDR2 modules

[Altera_Forum]

Hi, I have an application where we'd like to have a single FPGA driving 4x unbuffered (240 pin) DDR2 memory modules. To keep the FPGA pin count low I'd like to buffer only the Address/Control lines to each module but have the datalines common across all 4 modules. As we're not concerned about data transfer speed I can clock the DDR2 modules at the lowest allowable speed (125MHz) which would certainly help in meeting timing specs given the extra bus loading. Typically DDR2 only allows for 2 unbuffered modules to share a databus (not the 4xmodules I'm hoping for) - but then again they're usually run at high speed. 

 Does anyone have any suggestions/recommendations?     Many thanks.

[Altera_Forum]

Apart from the question, if the databus capacitive load may be too high, I don't exactly understand the purpose of this circuit. When sharing the databus, why not sharing the other control signals, execpt for chip enable?  

 As another point, the DDR2 controller cores don't support driving any signal execpt clock to multiple DDIO pins. It would be possible to my opinion, but most likely requires changes to the core code.

[Altera_Forum]

The purpose of buffering the address lines & control lines (RAS,CAS,WE) is that as each address/control line goes to each chip you're potentially looking at a load of 16 per module (16 chips/module) x 4 modules=> 64 loads.  

 The data bus on the otherhand only goes to 2 chips on each module, therefore there is a total load of (2 chips/module )x4 modules=> 8 loads.   Buffering the databus is somewhat more difficult as it's obviously bidirectional and besides I'm not aware of any DDR2 bidirectional buffers.   As for the DDR2 controller I'll write up my own core (as speed isn't an issue it should be fairly straight forward).   Thanks.

[Altera_Forum]

The essential point is that all DDR2 signals are generated by DDIO cells, thus buffering would always mean multiplying these DDIO cells rather than adding another buffer. The same can be basically done with bidirectional data, additional limited by the available number of DQ pins. When designing your own core, you should be free to arrange address and data lines according to your needs. 

 I see the point of high capacitive load, however if it works with two modules at high speeds of 200 MHz and more, it can work with four at 125 MHz.

[Altera_Forum]

It might be worth investing in the Mentor Graphics Hyperlinx tool set to model this interface. 

 Then you will know if it will work or not.  Avatar