FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6670 Discussions

Dual Data rate transmission

Altera_Forum
Honored Contributor II
1,097 Views

Hi All, 

 

I have one device which is transmitting and receiving data at both clock edge ( falling and rising edge ).  

 

Any one have concept of designing this type of module which tx and rx data at both edge of clock ? 

 

Thanks in advance 

 

Regards, 

Hardik Sheth
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
383 Views

Hi Hardik, 

you can use the megafunctions ALTDDIO_IN and ALTDDIO_OUT to handle double data rate transmission.
0 Kudos
Reply