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Hello everyone,
I want to dynamic reconfigure a partition of my design. I have followed these steps so far: a) make a revision of my project and assign the different personas for each revision. b) make a region and enable the partial reconfiguration option from Logiclock Region window c) make a partition for my re-configurable part and enable the multiple personas for this region d) instantiate IP Partial Reconfiguration as internal host. I don't know what to do next! Please could anyone provide some instructions for the DPR IP used as internal host? Thanks in advance.- Tags:
- Stratix® V FPGAs
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Hi Onoufrios,
did you already managed to convert .msf abd .sof to the partial rbf files? This is how i do within a POST_FLOW_SCRIPT_FILE:
set path "output_files"
set binaries "${path}/rbf"
file mkdir ${binaries}
set start_point x40y2
run_cmd "quartus_cpf
-p $path/${revision}.${start_point}.msf
$path/${revision}.sof
$path/${revision}.${start_point}.pmsf"
set options ""
# lappend options "-o use_scrub=on"
# lappend options "-o enhanced_bitstream_compression=on"
# lappend options "-o bitstream_decompression_during_pr=on"
set target_file "$binaries/${revision}.${start_point}.rbf"
run_cmd "quartus_cpf
-c $path/${revision}.${start_point}.pmsf
${target_file}"
The PR IP has two Registers, PR_CSR and PR_DATA. [LIST] set PR_CSR to 0x1 (start single clock PR) [/LIST] [LIST] copy partial rbf to if->PR_DATA register [/LIST] [LIST] check PR_CSR for status [/LIST] I guess you know this document already: https://www.altera.com/en_us/pdfs/literature/ug/ug-partrecon.pdf Additionally you need at least for CycloneV an extra PR license and you have to enable PR in quartus.ini. Don't know about StratixV.
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--- Quote Start --- Hi Onoufrios, did you already managed to convert .msf abd .sof to the partial rbf files? This is how i do within a POST_FLOW_SCRIPT_FILE:
set path "output_files"
set binaries "${path}/rbf"
file mkdir ${binaries}
set start_point x40y2
run_cmd "quartus_cpf
-p $path/${revision}.${start_point}.msf
$path/${revision}.sof
$path/${revision}.${start_point}.pmsf"
set options ""# lappend options "-o use_scrub=on"# lappend options "-o enhanced_bitstream_compression=on"# lappend options "-o bitstream_decompression_during_pr=on"
set target_file "$binaries/${revision}.${start_point}.rbf"
run_cmd "quartus_cpf
-c $path/${revision}.${start_point}.pmsf
${target_file}"
The PR IP has two Registers, PR_CSR and PR_DATA. - set PR_CSR to 0x1 (start single clock PR)
- copy partial rbf to if->PR_DATA register
- check PR_CSR for status
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Someone needs to write the partial rbf to the IP, this could be a Nios or HPS System, or a simple statemachine from internal/external ROM.
As the StratixV has up to 2640 M20k Blocks you may be able to store one small PR partition :-). A freeze wrapper would be a good design, but just for bench testing it works also without.- Mark as New
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Thanks for your info, unfortunately I stuck again.
I tried today to convert the .rbf file to hexout memory file, in order to store it in a memory(ROM) and I could not find the way. Do you know how to convert it?- Mark as New
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I would prefer a mif file, the format is very easy.
A simple Matlab example is shown here, this could be easily ported to C, tcl, ... http://www.alteraforum.com/forum/showthread.php?t=27934 You can also use srec_cat from the srecord Tools: srec_cat dummy.rbf -binary -o dummy.mif -Memory_Initialization_File I don't know if Altera provides a Tool for this simple task. I would use a small tcl loop, which can be easily started automatically during the build.- Mark as New
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--- Quote Start --- I would prefer a mif file, the format is very easy. A simple Matlab example is shown here, this could be easily ported to C, tcl, ... http://www.alteraforum.com/forum/showthread.php?t=27934 You can also use srec_cat from the srecord Tools: srec_cat dummy.rbf -binary -o dummy.mif -Memory_Initialization_File I don't know if Altera provides a Tool for this simple task. I would use a small tcl loop, which can be easily started automatically during the build. --- Quote End --- I have a Stratix V GX Transceiver Development Kit. This board has a MAX CPLD device to configure the FPGA from a flash memory. As far I know the PFL (Parallel Flash Loader) IP does not support .rbf files. Do you know how can I implement the DPR from the flash memory? Any ideas? Thanks a lot for you help. Onoufrios
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Hi Onoufrios,
sorry, i do not use Stratix. Can't you use a Nios as internal host and just copy the Data from the Flash?- Mark as New
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--- Quote Start --- Hi Onoufrios, sorry, i do not use Stratix. Can't you use a Nios as internal host and just copy the Data from the Flash? --- Quote End --- Thanks for your feedback. From the design's requirements I cannot use the internal host feature in the DPR IP. The device should be reconfigured from the IO Reconfiguration Pins. For any further suggestion please answer to my post. Onoufrios

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