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Hi,

I am working at implementing a bandpass FIR filter on MAX 10 FPGA development kit. So, I am taking a signal input from the SMA connector into the ADC (1Msps, allowed input clock levels 2, 10, 20, 40, 80Mhz ) followed by a FIR filter block (MATLAB generated HDL) a Parallel to Serial Converter which is connected to the on board DAC (30MHz). Since the DAC has a 24 bit shift register, the clock frequency for ADC and all blocks in between would be 30/24 = 1.25Mhz at max. This not possible with the ADC constraints. The other way around, with 2MHz for the ADC, the DAC would need 48 MHz which is well beyond its maximum range. Where am I going wrong? or is implementing a real time FIR system with these specifications not possible with this board? If not would I have to relax the constraint on DAC and use an external DAC through a PMOD extension? In this case how must i proceed with the design? I'd appreciate any help I can get. Thanks in AdvanceLink Copied

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first you say 1Msps but various clock rates. So I guess your wanted sampling is 1Msps. This means(to me)you are oversampling by 2 f your ADC clock is 2

can't you downsample from 2 to 1 then DAC will be at 24Mhz- Mark as New
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What does your ADC say about its digital output (you said it gives 1Msps) but what clock does it give you. Remember ADC may have its own internal clock but what matters to you is the clock rate given to you and normally it is same as data rate i.e. 1MHz.

If you have DDR interface it will be 0.5MHz to give you 1Msps- Mark as New
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