E-Tile frequency constraints

[MichaelB]

Hi,

I've a question regarding the E-Tile transceiver and their constraints.

I would like to implement different data rates which I have already tested successfully using the reconfiguration interface.

Now I'd like to ask if it's necessary to create a constraint for the minimum and maximum frequency.

My intention would be to instantiate the E-Tiles with a lower data rate and create constraints for the minimum and maximum frequency used for RX/TX_out_clock.

I already tried it with the create_clock constraint to create it with their periods but obviously the values are truncated.

Can I specify ps or fs instead of ns for the clock period?

Another possibility would be:

Should I specify the highest data rate and the lower ones will be possible without timing violations, too?

Which 'strategy' would be the better one to avoid any issues with the E-Tiles during operation?

Best regards,

 Michael

[CheePin_C_Intel]

Hi,

Please correct me if I am wrong, as I understand it, your specific inquiry is related to the tx/rx output clock constraint for different data rate. If yes, please allow me some time to consult our timing expert on this to if there is any guide or documentation on multi data rate constraint. For your information, I am more towards transceiver PHY and hardware instead of timing.

Just would like to check with which specific parallel output clock of Native PHY that you are trying constrain?

Please let me know if there is any concern. Thank you.

[MichaelB]

Hi CheePin,

thanks for your response!

Yes I'm referring to the parallel data clock (tx/rx out clk) of the Native PHY.

Best regards,

 Michael

[CheePin_C_Intel]

Hi Michael,

For your information, I have just received a response from our timing team on the multi frequencies constraint. You may refer to the following timequest cookbook -> example 10 on using clock groups to constraints the same port with different frequencies.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf

Please let me know if there is any concern. Thank you.

[MichaelB]

Hi CheePin,

thanks for the document.

I already tried to constraint the clock like in example 10 but I was not able to hit the frequency correctly.

Due we are using high frequency I'd like to know if there is a possibility to switch to ps or fs for time scale.

Might this be an issue if I define them not accurate enough?

Is it necessary to define the frequency if I define the highest one per default? Can I assume that the lower frequencies are functional as well?

Best regards,

 Michael

[CheePin_C_Intel]

Hi,

Thanks for your update. Please allow me some time to feedback your latest inquiry to our timing team for further assistance.

[Kenny_Tan]

Can you put down the sdc file that you have written?

Also, did you get timing violation?

I think the frequency that you are trying to archive is too fast. So, the constrain might not be applicable anymore as those constrain are for core but not periphery.

[MichaelB]

Hi Kenny,

thx for your response!

Constraints file:

create_clock -period 7.716049382716049 -name clk_high_freq [get_ports {u0|etile|*x_clkout|ch*}]

create_clock -period 20.83333333 -name clk_low_freq [get_ports {u0|etile|*x_clkout|ch*}] -add

At first those ports are not recognised for create_clock but for clock_groups it does which I don't get.

Furthermore the period will be truncated which makes me a little bit worried to hit the required frequency.

I'd really like to set the lower frequency as default (in IP file for data rate) and constraint the clocks to its maximum frequency.

Timing violations are not present right now because I used the lower frequency as default a create_clock constraint won't be recognised and is invalid because the port does not exists.

For create_clock_group it does work.

Do you have any hints how to solve the truncation and the create_clock to the given ports?

Best regards,

 Michael

[CheePin_C_Intel]

Hi,

Thanks for sharing your SDC constraint. It seems like you are target relatively high precision which I am not sure if TimeQuest will be able to recognize. I have had some discussion with Kenny, probably you can try to set something like "Create_clock 10ps... " to see if it works. Adding the "ps" suffix.

If it is not working, you might need to stick to the default "ns" time scale. Sorry for the inconvenience.

Please let me know if there is any concern. Thank you.

[MichaelB]

Hi CheePin,

alright I will do it another way. I will define the maximum data rate to get the highest frequency generated by Quartus in its E-Tile constraint files.

I can switch the data rate by PMA configuration which I've already tested & verified for my design.

Can I be sure that all lower data rates are working properly without defining a minimum frequency for the lowest data rate?

Best regards,

 Michael

[CheePin_C_Intel]

Hi,

As I understand it, constraining to the highest frequency does NOT guarantee that all lower data rate will work properly. It is recommended for you to use the previous clock group assignment to constrain for different frequencies.

Please let me know if there is any concern. Thank you.

[MichaelB]

Hi,

alright I will create a constraint for highest and lowest frequency.

Is there any recommended constraint to use? Should I use create_clock on a specific port of the E-Tile native or can I use create_generated_clock?

I already tried it with the create_clock with the specific output clocks of the E-Tile native but this statement won't be recognised. The port name is not available in the technology map. 

Could you help me which port I should constraint here?

Kind regards,

 Michael

[CheePin_C_Intel]

Hi,

Based on my understanding, normally we would constraint the input XCVR refclk and the TimeQuest should be able to auto-populate the PLL derived clocks. For previous device family, we need to add a derive_pll_locks SDC but I think for S10 device, it is no longer needed. Can you try constraining the refclk and check if the parallel output are auto-populated?

Thank you.

[MichaelB]

Hi,

I'm planning to use the same reference clock for all configurations. To achieve the different data rates I'm just programming the PLL multiplier value using the Avalon reconfiguration interface.

Do I have to set the constraint to the PLL output of the XCVR?

Best regards, 

 Michael

[CheePin_C_Intel]

Hi,

Thanks for your update. In this case, I think you should constrain the PLL output clock frequencies as TimeQuest might not be aware of your target reconfiguration frequencies.

[CheePin_C_Intel · Accepted solution]

Hi,

If you observe issue trying to constrain the output clock ie cannot find in tech map, would you mind to help opening a new Forum case and let me know the case. I will help to route to our timing team to better assistance. Thank you.

[MichaelB]

Hi,

thanks for your help!

I have created a new thread for the E-Tile tx/rx out clock constraint here:

https://community.intel.com/t5/FPGA-Intellectual-Property/E-Tile-TX-RX-out-clock-constraint/m-p/1269151#M23602

Best regards,

 Michael

[CheePin_C_Intel]

Thanks for your help. I have routed the case to the timing expert and ping them through email as well.

[CheePin_C_Intel]

Hi,

As I understand it, our timing team is currently assisting you in the new case. We shall continue to follow up with you in the new case. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.