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5918 Discussions

EMIF controller and DDR4

User1580871742356367
357 Views

Like to confirm who's programming the DDR4 MMR registers. 

The Memory controller engine alone(without SW or SW (e.g. uboot etc.) ? Thanks. 

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5 Replies
SimonRichter
New Contributor I
348 Views

The initial configuration is done by the memory's sequencer block, from the IP settings, so in the simple case, you don't need to use this interface at all and you can disable it.

U-Boot could use these registers during a memory test, and the operating system could use those registers to detect ECC errors at runtime, so if that is desired, you'd connect the interface to the soft CPU's data bus.

AdzimZM_Intel
Employee
339 Views

Hi Sir,


Thanks Simon for providing the explanations.


The Memory Mode Register (MMR) interface is the Avalon based interface through which core can access debug signals and sideband operation requests in the hard memory controller.


Do you have further question about this?


Regards,

Adzim


User1580871742356367
330 Views

Yes, I have one more question, where was the arf_to_valid parameter or value got from by Quatus Pro. 

I mean which timing settings in the EMIF generator. 

I didn't see it in the emif.xml nor hps.xml. 

AdzimZM_Intel
Employee
315 Views

Hi Sir,


I believe that the timing parameter setting is at the tRFC.

tRFC is refers to the Refresh Cycle Time where the amount of delay after a refresh command before an activate command can be accepted by the memory.


Thanks.

Adzim


AdzimZM_Intel
Employee
250 Views

Hi,


I hope your doing well.


It's been a while since my last feedback.


I just want to remind you here incase you have some questions to ask further.


Thanks,

Adzim


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