Enable the Latency Measurement function of Stratix 10 E-tile Transceiver Native Phy

[Spark_Wang]

Hi,

I want to use the Latency Measure function,I enabled the two options shown in the figure.

And then this ip adds these ports(below the picture)

The first question:

According to the user guide, if I want to use this feature, don't I need to connect these ports?

(the description shows do not connect)

In addtion,This ip provides a deterministic delay measurement method, as well as the calculation formula, and my former colleague consulted your FAE to explain these parameters

I need to read the values of these cpri phy registers to get these delay parameters

We can read these values through the reconfig avmm interface.

the problem is that the 32bit of the reconfig_avmm interface corresponds to 4 channels (8bits each).

But the data in this cpri phy register is 32bit.

[Spark_Wang]

James Murray(European Application Engineering),Is he still at intel? Because I saw his e-mails with my former colleagues.

thank you))

[LeoFeng]

Hi Wang,

This is Leo. 

For the first question, the latency measurement ports are for internal use only, the user should not enable it.

That's why those ports are reserved ports and should not be connected.

For the second question, according to E-tile CPRI PHY IP UG. The reconfig_addr is 19-bit per channel, reconfig_readdata is 32-bit per channel. So each channel will have a total 32 bits data bus instead of 8 bits each.

Best regards,

Leo Feng

[Spark_Wang]

Hi,Leo

Thanks for your help.

We are using the stratix 10 E-tile Transceiver Native phy ip core, and we have enabled latency measurement options.

but for this ip(stratix 10 E-tile Transceiver Native phy ip )the  reconfig_readdata is 8-bit per channel.

I used four channels,so the reconfig_readdata is 32-bits.

Because we want to use latency measurement.

[Spark_Wang]

Hi,Leo

-----------For the first question, the latency measurement ports are for internal use only, the user should not enable it.

That's why those ports are reserved ports and should not be connected----------

We need to use this latency measurement function, open this port, and then we can read the relevant values through the reconfig interface, right?

[LeoFeng]

Hi Wang,

I think I figure out the gap between what we are talking about.

The deterministic latency calculation of E-tile CPRI PHY IP is used when you are using CPRI PHY IP instead of Native PHY IP.

For deterministic latency calculation of E-tile CPRI PHY IP, you will need to read different registers from different avmm interfaces.

For example, TxDL is read from CPRI PHY register which is through CPRI PHY reconfiguration interface(32-bit). 

This interface is not the reconfiguration interface(8-bit) you saw on Native PHY IP.

If you're only using Native PHY IP, you can only get the DL from deterministic latency measurement interface. Those calculations are not applicable.

Best regards,

Leo Feng

[Spark_Wang]

Hi,Leo

thanks for your reply

yes,we are using the Stratix 10 E-Tile Transceiver Native PHY.

On the configuration interface, when we enable latency measurement options, the interface shown in Table 45 is added to the ip core.

But the description says " Reserved port. Do not connect. "and the comment (28) in Table 45 suggests referring to the latency measurement section.So we don't know how to use this latency measurement options.

We are using Stratix 10 E-Tile Transceiver Native PHY, can you provide a solution to measure deterministic latency based on Stratix 10 E-Tile Transceiver Native PHY?