Good evening from Japan,I'm having endless trouble getting HDMI output to work on my Arria10 ALARIC (ReflexCES) development board, Bitec HDMI output FMC card and Bitec HDMI IP core. I'm generating a test image at 1920x1080 using Altera VIP IP and outputting it via a CVO to the HDMI IP core. My pixel clock is running at 74.25MHz (1/2 x 148.5MHz) in TMDS 2-symbol mode, in order to output at a frame rate of 60Hz. DVI compatibility mode is ON, scrambling and all other HDMI 2 features are OFF. My transceivers are running at 3712.5MHz and I'm oversampling the data from the HDMI IP core to the transceivers 10 times to get the right clock rate. The scope output for my clock signal (top) and red channel (bottom) below is the result: http://www.alteraforum.com/forum/attachment.php?attachmentid=11940&stc=1 In principle that looks alright to me, but.. When feeding the output into another development board with a Bitec HDMI RX core, the receiver PLL locks and I get a RX ready signal, but no image (via Quartus debug monitor). If I connect directly to a monitor, I get no signal. If I double the transceiver rate, I get a warning from my test display that I'm outputting at 120Hz, which is not supported. Correct wiring and signal output of clock, r, g, b have been verified. This is probably not enough information for anyone to find concisely what is wrong, but in case anyone has a hint or some experience with this, it is highly appreciated. Also I was wondering, if maybe my base PLL clock generation is not accurate enough. E.g. as pixel clock I'm not generating exactly 74.25MHz, but rather 74.24Mhz. Is that off too much so that the monitor doesn't detect correct timing anymore? Thank you, Klaus
Well, yes, we purchased the IP core and I'm in contact with Bitec in order to resolve the issue. But somehow it is not progressing. I asked on the forum, just in case someone else has had the exact same problem and might have a quick fix. Although admittedly the probability of that plus that this particular person also sees my post is relatively low :-) Thank you for your answers, though!
In the end the problem was solved thanks to support from Andy@Bitec. There was a problem with the clock driving the TPG and HDMI core part of the design. I used independent clocks to drive my TPG and HDMI core, but should have used the output clock from the transceiver directly. Doing that it worked right away. Yeiii!!!