I have a design instantiating two clock buffers (ALTIOBUF). The design synthesizes fine in Synplify Pro, but when I compile the netlist in Quartus Prime Lite, I get the error: Error (12006): Node instance "clk_buf_altclkctrl_0_sub_component" instantiates undefined entity "clk_buf_altclkctrl_0_sub_0".
I've included the files 'clk_buf.v' (my top-level buffer) and 'clk_buf_altclkctrl_0.v' in my Synplify project.
Is there a file(s) that is supposed to be included in Quartus?
I've included the .qip file. Not sure what you mean by "Instantiate ALTIOBUF..." Using the IP tool I created a module called "clk_buf"; THAT is instantiated at the top leve:
//clock buffers clk_buf CK_MAIN ( .inclk (clk_in), .outclk (clk) ); clk_buf CK_SPI ( .inclk (spi_clk_in), .outclk (spi_clk) );