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BVola
Beginner
271 Views

Error 12006 when compiling clock buffer

I have a design instantiating two clock buffers (ALTIOBUF). The design synthesizes fine in Synplify Pro, but when I compile the netlist in Quartus Prime Lite, I get the error: Error (12006): Node instance "clk_buf_altclkctrl_0_sub_component" instantiates undefined entity "clk_buf_altclkctrl_0_sub_0".

 

I've included the files 'clk_buf.v' (my top-level buffer) and 'clk_buf_altclkctrl_0.v' in my Synplify project.

 

Is there a file(s) that is supposed to be included in Quartus?

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5 Replies
AnandRaj_S_Intel
Employee
83 Views

Hi Barry,

 

  1. Include .qip file in quartus.
  2. Instantiate ALTIOBUF in top level file.

 

Regards

Anand

BVola
Beginner
83 Views

I've included the .qip file. Not sure what you mean by "Instantiate ALTIOBUF..." Using the IP tool I created a module called "clk_buf"; THAT is instantiated at the top leve:

 

//clock buffers clk_buf CK_MAIN ( .inclk (clk_in), .outclk (clk) );   clk_buf CK_SPI ( .inclk (spi_clk_in), .outclk (spi_clk) );

 

AnandRaj_S_Intel
Employee
83 Views

please share the project.

BVola
Beginner
83 Views

Apparently, I don't need to instantiate clock buffers; the tool automatically adds them. Is that correct?

AnandRaj_S_Intel
Employee
83 Views

Yes,Please share the project? for further support

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