hi,1. I generate one Low latency Ethernet 10G MAC IP with the mode "10GBASE-R Register Mode Example Design arria 10". As the generated tx_serial_data/rx_serial_data pin in the IP's input/output is single-ended, I think I need to use a differential IO pin in my top design . so I insert one differential BUF for it before it is connected to the Low latency Ethernet 10G MAC IP core. fbm_ibuf_multichan u_fbm_ibuf_multichan ( .dout ( rx_serial_data ), // dout.export .pad_in ( rx_serial_data_p ), // pad_in.export .pad_in_b ( rx_serial_data_n ) // pad_in_b.export ); fbm_obuf_multichan u_fbm_obuf_multichan ( //input .pad_out_b ( tx_serial_data_n ), .pad_out ( tx_serial_data_p ), .din ( tx_serial_data ) ); then tx_serial_data/rx_serial_data is connected to the Low latency Ethernet 10G MAC IP core. 2. I am using DEVICE 10AX115U4F45I3SGE2 3. the pin assignments for tx_serial_data /rx_serial_data are: (BANK GXBL1E) set_location_assignment PIN_AN42 -to tx_serial_data_p set_location_assignment PIN_AN38 -to rx_serial_data_p But I meet Error in the Fitter(as shown below) So my question is: 1) why the pin of tx_serial_data/rx_serial_data in the generated Low latency Ethernet 10G MAC IP core is single-ended? 2) Is it correct to connect one differential BUF for it? 3) How to fix this error? Error (175001): The Fitter cannot place 1 HSSI_PMA_TX_BUF. Info (14596): Information about the failing component(s): Info (175028): The HSSI_PMA_TX_BUF name(s): hft_ethernet_multichan:u_hft_ethernet_multichan|altera_eth_10g_mac_base_r_low_latency_wrap:packet_div_channels.i_u_altera_eth_10g_mac_base_r_low_latency_wrap|low_latency_baser:baser_inst|low_latency_baser_altera_xcvr_native_a10_161_dsfdwxi:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts.twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5es2:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5es2:inst_twentynm_pma|gen_twentynm_hssi_pma_tx_buf.inst_twentynm_hssi_pma_tx_buf Error (16234): No legal location could be found out of 96 considered location(s). Reasons why each location could not be used are summarized below: Error (175006): Could not find path between source pin and the HSSI_PMA_TX_BUF Info (175026): Source: pin rx_serial_data_p Info (175015): The I/O pad rx_serial_data_p is constrained to the location PIN_AN38 due to: User Location Constraints (PIN_AN38) Info (14709): The constrained I/O pad is contained within this pin Info (175021): The pin was placed in location pin containing PIN_AN38 Error (175022): The HSSI_PMA_TX_BUF could not be placed in any location to satisfy its connectivity requirements Info (175029): 95 locations affected Info (175029): HSSIPMATXBUF_1C0 Info (175029): HSSIPMATXBUF_1C1 Info (175029): HSSIPMATXBUF_1C2 Info (175029): HSSIPMATXBUF_1C3 Info (175029): HSSIPMATXBUF_1C4 Info (175029): HSSIPMATXBUF_1C5 Info (175029): HSSIPMATXBUF_1D0 Info (175029): HSSIPMATXBUF_1D1 Info (175029): HSSIPMATXBUF_1D2 Info (175029): HSSIPMATXBUF_1D3 Info (175029): HSSIPMATXBUF_1D4 Info (175029): HSSIPMATXBUF_1D5 Info (175029): and 83 more locations not displayed Error (175003): The HSSI_PMA_TX_BUF location is occupied (1 location affected) Info (175029): HSSIPMATXBUF_1E0. Already placed at this location: HSSI_PMA_TX_BUF tx_serial_data_p~output_PMA_TX_BUF_FITTER_INSERTED Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.