The device is the 5CGXFC9C7F23C8 and the Quartus version 17.1 is used.
The Avalon-MM CV Hard IP for PCIe is configured as Gen1 x4.
The Custom PHY component has one lane in Duplex mode enabled. (The goal is to use two lanes in Duplex mode)
The two IP Cores share one Reconfiguration Controller.
The analysis & synthesis is running without any errors but the fitter gives me following error message:
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 Channel PLL(s)).
Looking in the Resource Usage Summary of the a&s this makes sense, because it shows that 7 Channel PLLs are being used. When trying without the Custom PHY it shows that 5 Channel PLLs are used. (The device has 6).
As far as I understand, the PCIe Core uses 5 becuase of: "one for the TX PLL and one for the channels" (from this document ).
Why is that? The figures 7-37 and 7-38 in the document above make it seem as if one additional channel PLL (1 or 4) was used for clock generation (TX PLL) for the other transceiver channels and their local PLLs. Is that correct?
Further reading revealed that the Custom PHY Core has the same needs in regard of PLLs.
My conclusion to this is, that I need a FPGA that has more Transceiver channels available (at least 8, so probably one that has 9)
Is this correct or is there any other way to implement even one of the two Duplex lanes of the Custom PHY Core? Is it possible to somehow share some resources or place the TX PLL "inside" the FPGA (for slower interfaces) ?
As you have probably mentioned I am pretty new to using Intel FPGAs transceiver interfaces, but I am doing my best trying to understand them.
no problem; I appreciate your response anyway!
The observations I made in the meantime together with your reply have arisen a few new questions for me:
1) You mention, that - with the given configuration - it should be possible to place the PCIex4 together with one duplex channel in the FPGA. I could not find a suitable placement for the pins to work out this way. Are there any more constraints regarding the pins being used here?
2) When defining a PLL as a fPLL, how does one enable the Custom PHY to use that fPLL's clock as the transmitter clock? The PHY does not seem to have a option regarding this.
At the moment I am most likely to use a small Arria10GX device (12 transceiver channel) for the application. I hope to be able to put at least a PCIe Gen3 x4 (best case x8) and three duplex channels in that device, but I have to read into that more to come to a decision or ask detailed questions.
1) + 2) Thank you very much, that cleared a lot things up for me! Where does one find the information you provided? I feel like I went through the whole internet.
3) Do you know where I can read about the PLLs needed for PCIe Gen3 x8? Does this configuration need 9 Channel PLLs or 1 extra per 4 Lanes, which would sum up to 10?
4) Does the fPLL data rate (3.125 Gbps) you mentioned above also apply to the Arria 10 devices? Based on that information it should be possible to use it for 2125 Mbps links but not for interfaces like 10 GigE.