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Altera_Forum
Honored Contributor I
786 Views

Error (171172): Detected conflicting assignments - for clock input

Hi, 

 

I created a design in DSP Builder and generated the QIP and VHDL files. I then included the top level VHDL file in a Verilog file in order to make port and DAC connections on the DE4 board. 

 

When I compile the design, I am getting this error if I am trying to assign PIN_A21 or any other clock pins to the input clock port. I am able to assign all other pins except the clock. 

 

Please let me know how can I resolve this error. 

 

Thanks.
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Altera_Forum
Honored Contributor I
40 Views

Got it resolved.

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