FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Error: SOPC Builder

Altera_Forum
Honored Contributor II
944 Views

Hello! 

 

I am working with VIP Suite. I am getting the following error in between Chroma resampler and Deinterlacer. 

 

The error message is - 

 

Error:alt_vip_dil_1.dout/alt_vip_csc_1.din: The source has 1 symbol per beat while the sink has 3 . 

 

and also similar kind of error in between deinterlacer and csc. 

 

Error:alt_vip_crs_1.dout/alt_vip_dil_1.din:The source has 3 symbols per beat while the sink has 1.  

 

 

Can any one will help me with this.. 

 

I will be very thankful to him/her.
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
164 Views

I'm not familiar with those cores but I'll explain what the messages mean. In ST you have beats which are cycles where valid data is being transferred. In each beat you can have multiple symbols of data. For example if I was moving RGB video data with 8 bits per colour (symbol) then I would setup my streaming port to be 24 bits width with 8 bits per symbol (so 3 symbols per beat). 

 

So what the message means is that the deinterlace component is setup to send out a symbol that is as wide as the source interface. Meanwhile the CSC hooked up to the other side is expecting three symbols of data to be received on it's sink interface. When connecting streaming cores it is very important that the symbol size is consistent since this is what the tools use to perform data format adaptation (wide to narrow or narrow to wide). 

 

If you are familiar with memory mapped systems it is similar to hooking up a master to a slave where each one has a different byte size. If my master thought a byte was 9 bits and my slave thought a byte was 7 bits then that would become a mess to deal with. Beats are similar to transfers and bytes are similar to symbols.
0 Kudos
Reply