Error: (vsim-3033), Error Loading Design

[mwac__]

I'm trying to generate a clock of 20 MHz from altera IP core. I've instantiated the IP Core in my top level design and wrote a test bench. When I try to simulate the design the error can be seen in the transcript window.

The error is of vsim3303. Instantiation of 'altera_pll' failed. The design unit was not found.

Concerned files are attached for convenience. Do let me know if any other information is required.

Thank You.

[KennyTan_Altera]

All the simulation now run in the msim.tcl as they include all the necessary lib to be compile, for the full steps, you can follow: 1.1. Prerequisites , remember to click on the bottom for the next steps.

[KennyTan_Altera]

I have tested this without any error.

[KennyTan_Altera]

Is there any further question?

[KennyTan_Altera]

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