Error: (vsim-3033) Instantiation of 'msgdma' failed. The design unit was not found.

[VCham]

I get this error when I try to simulate in ModelSim Altera Starter Edition 10.3c

This is my first time simulating a Qsys block in ModelSim.

I have successfully completed the following steps:

1. created Qsys block containing 2 MSGDMAs and 1 clock source
2. created ModelSim project and test bench which instantiates Qsys block and a user submodule
3. generated Qsys simulation files and exported them to the ModelSim source directory
4. ran mentor.do according to the generated msim_setup.tcl

The generated simulation folder contains a submodule folder with all the .v files for the Qsys IP blocks. When I run "mentor.do", a Libraries folder shows up in the source directory. When I try to simulate my test bench I get the following error:

Error: (vsim-3033) simulation/msgdma_fifo_manager.v(61): Instantiation of 'msgdma_fifo_manager_msgdma_0' failed. The design unit was not found.

# 

#     Region: /depth_engine_tb/u0

#     Searched libraries:

#      /sim/top/depth_engine/libraries/work

Any help would be appreciated.

[AnandRaj_S_Intel]

Hi @VCham​ ,

Can you share the design ?

Which version &edition of quartus & modelsim are you using ?

Attache modelsim log.

Regards

Anand

[VCham · Accepted solution]

I am using ModelSim Altera Starter Edition 10.3c. 

I am also compiling within ModelSim but the Qsys project was created using Quartus Prime Version 17.0.2.

As an update, I realized that the way I defined the TOP_LEVEL_NAME in the mentor. do file was incorrect. Which meant it prevented the msim_setup.tcl script from running the simulation. And when I then went and tried to run the simulation manually, I was doing so without the library inclusions that the tcl script uses.

vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L write_mstr_internal -L read_mstr_internal -L dispatcher_internal -L rst_controller -L msgdma_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME

Since it was hard to find information online for how to define these variables, the definition that finally worked was

set TOP_LEVEL_NAME work.user_module_tb

I am now able to simulate. I get warnings that may have to do with the fact that my test bench is still incomplete, but otherwise the MSGDMA is simulating properly.