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How to use Intel serial flash loader IP core with Cyclone 10 lp development kit


I want to make a .sof file containing the  Intel serial flash loader IP.

Then I want to program the fpga with this .sof file, and after that, program the EPCQ64 of the development kit with a .jic file containing my system.


I'm confuced when it comes to how I connect the fpga pins to the Serial flash loader ip.


The inputs/outputs of the flash loader looks like this:

module FlashLoader (

input wire asdo_in,       //       asdo_in.sdoin

input wire asmi_access_granted, // asmi_access_granted.asmi_access_granted

output wire asmi_access_request, // asmi_access_request.asmi_access_request

output wire data0_out,      //      data0_out.data0out

input wire dclk_in,       //       dclk_in.dclkin

input wire ncso_in,       //       ncso_in.scein

input wire noe_in        //       noe_in.noe



I know you can program the .jic file to the EPCQ64 using quartus programming tool which seems to program the fpga with a serial flash loader. However, I want to do this manually for better understanding and to be able to make scripts for the programming.


There might be something fundamental I do not understand since I'm new to both FPGA and quartus.

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1 Reply
Hi Hans, The connection is depending on the IP itself. I would suggest you to start with our user guide which is available at link below: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf It shows the steps to connect the IP in FPGA and also the steps to have it configured. Furthermore, you may also refer to our how-to-video: https://www.youtube.com/watch?v=dPSFCGNQOCU Hope it helps. Regards, YL