FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5988 Discussions

Error with clock connections to DDR2

Altera_Forum
Honored Contributor II
1,298 Views

This is a Cyclone IVe design, using Quartus 17.0  

 

I have a qsys system where I have instantiated the DRAM controller "DDR2 SDRAM Controller with ALTMEMPHY" 

 

When I try to run analysis / synthesis I got this error: 

Error (13059): The DDIO_OUT WYSIWYG primitive "core:core1|core_ddr2:ddr2|core_ddr2_controller_phy:core_ddr2_controller_phy_inst|core_ddr2_phy:core_ddr2_phy_inst|core_ddr2_phy_alt_mem_phy:core_ddr2_phy_alt_mem_phy_inst|core_ddr2_phy_alt_mem_phy_clk_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_n5h:auto_generated|ddio_outa[0]" feeding the pin "ddr2_clk" has multiple fan-outs 

 

My qsys block is named "core". The only connections to the ddr2_clk are to the module port of the "core" module, and then it is an output port of the top level module. It does not connect anywhere else. 

 

 

As an experiment I left the port disconnected. then I got this error: 

Error (15873): Output port DATAOUT of DDIO_OUT primitive "core:core1|core_ddr2:ddr2|core_ddr2_controller_phy:core_ddr2_controller_phy_inst|core_ddr2_phy:core_ddr2_phy_inst|core_ddr2_phy_alt_mem_phy:core_ddr2_phy_alt_mem_phy_inst|core_ddr2_phy_alt_mem_phy_clk_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_n5h:auto_generated|ddio_outa[0]" must drive input port I of an I/O OBUF primitive. It currently drives "core:core1|core_ddr2:ddr2|core_ddr2_controller_phy:core_ddr2_controller_phy_inst|core_ddr2_phy:core_ddr2_phy_inst|core_ddr2_phy_alt_mem_phy:core_ddr2_phy_alt_mem_phy_inst|core_ddr2_phy_alt_mem_phy_clk_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_n5h:auto_generated|input_cell_h[0]" 

 

 

 

 

So I noticed that it specified that the signal must be connected to an I/O port. I had previously connected it to an "output" so I changed it to be an I/O port. Back to the same error I started with. 

 

 

can anyone tell me what the problem is? 

 

Rod
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
177 Views

Hi Rod, 

 

Here are some DDR2 example design , you can refer to the connection of these example designs and apply the same to your design. 

 

http://www.alterawiki.com/wiki/design_example_-_cyclone_iii_ddr2_sdram_altmemphy_167mhz_x32 

http://www.alterawiki.com/wiki/design_example_-_stratix_iii_ddr2_sdram_uniphy_400mhz_x72 

 

 

(This message was posted on behalf of Intel Corporation)
Reply