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Evaluation of the latency of each module on my design

Altera_Forum
Honored Contributor II
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Hi, 

In order to know how fast is my FPGA Stratix II 2SEP2S180F1020C3, I would like to evaluate the latency of my design on Alera Dsp Builder. I read that an approach is to obtain the latency of the arithmetic operators (multiplier, divider, parallel adder, gain) before evaluating the delay for each module. How can I do it? 

 

I also read about "Implementing Multipliers in FPGA Devices" on the site http://www.altera.com/literature/an/an306.pdf, but I'm still confused. 

 

So, I would also like to Know how I can use Dsp Builder to obtain the critical path or longest time between the input and the output of the data through the design. 

 

Thanks
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Altera_Forum
Honored Contributor II
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You will need to synthesize your design with Quartus II and use timequest afterwords to analyze timing and detect the critical paths.

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