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Valued Contributor III
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External Avalon MM interface

Hi all, 

I need to interface a microporcessor external to fpga to a Nios system using a shared memory. 

So, I thought to use a onchip memory module in dual port configuration which will be accessed by Nios on one side and by the external system on the other side. 

My external device can possibly emulate Avalon signals, but a simple bus interface (addr, data, cs, rd, rw) would be much more convenient. 

How can I do this with sopc builder? 

Is there any bridge device available to perform this function? 

Sopc builder requires a Avalon bus master connected to the onchip memory port which is supposed to be driven by my external device, so I can't generate the system. 

 

Regards 

Cris
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Valued Contributor III
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Hi Cris, 

 

You can refer to some examples provided at: 

http://www.altera.com/support/examples/nios2/exm-avalon-mm.html 

 

But it seems that it can add to some complexity of your design requirement. If so, you can take a look at options given in: 

http://www.altera.com/literature/hb/nios2/external_processor_if.pdf 

 

Please refer to p11 of above pdf file titled "Custom Bridge Interfaces". I think that it is the simplest method of having external processor accessing an SOPC builder system peripherals. 

 

Hope this helps. 

 

Cheers, 

BD
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Valued Contributor III
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Hi BD, 

Thank you for your answer. 

Both the solutions you suggested are feasible for my system. The one based on master template is much more complete and ready to integrate in sopc builder; I took a look at the example and documentation and I think I can easily use it. 

Anyway, I'd prefer something more simple, since I don't need to access the whole Avalon bus but only a small shared memory. 

Then, the second solution seems to be better for my case, but I'm not very expert in HDL coding and I never used the Component Editor. 

I think it should be an easy job but I fear I would lose a lot of time in learning all that stuff to extract the minimal information I need.  

Do you know if an example is available of the interface shown on page 12 of external_processor_if.pdf ? 

 

Cris
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Valued Contributor III
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FYI some time down the road I plan on replacing those master templates to be based on the masters from the modular SGDMA design example. To control those from outside of SOPC Builder will require an additional gasket to breakout the control signals. The master templates are a bit old and lack a bunch of features that the mSGDMA supports which is the reasoning behind the switch. 

 

If you want to give the modular SGDMA masters a shot send me a PM and I can give you early access to the bug fixes I just rolled in.
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