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**fft_bb.v, fft.vo, fft.v, fft_tb.v** (that have been generated by wizard) into it. Compilation process is OK, so I start simulation, append all signals from **fft_tb** instanse to Wave window. Then I make 'Run -all' command and wait for result. However, in spite of there is a** $finish** task in the testbench, simulation never stops. If I make forced stop of simulation, I see signals **source_valid, source_real, source_imag** being in a HiZ state all the way. This repeats regardless type of FFT (streaming, variable straming, so on) or number of points (64, 128, ... 4096,... etc). Of cource, there are no output text files with FFT results. CAD Quartus II 64-bit Web Edition 13.0 ModelSim ALTERA STARTER EDITION 10.1d FPGA Altera Cyclone IV E (EP4CE40F23) So, can anyone help how to test FFT function? Thanks

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07-08-2013
10:38 AM

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FFT MegaCore Function simulation in Modelsim never finished

Hi, everyone!

I'd like to ask those who deals with FFT MegaCore Function. My problem: I can't get generated FFT MegaCore Function simulation finished in Modelsim. I create a project in ModelSim, then append files
13 Replies

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Altera_Forum

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07-09-2013
12:00 PM

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Hello,

First, you should check all the inputs of the FFT in ModelSim, and be sure that no one is undefined. Second, you should check the output signal called source_error (the meaning is available in the user guide), it can give you the reason of your problem. Best regards, Jérôme
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**fft_tb.v** file and in the Wave window of ModelSim all inputs of FFT function instanse are connected and have definite values (St0, St1), while all the outputs (including **source_error**) signals are in HiZ state whenever I stop simulation. Anyway, I rely on this generated testbench file, which seems to be quite consistent. By the way, megafunction wizard generates MATLAB model, and it works fine. Did you ever try simulate this megafunction in ModelSim yourself? May be there is bug in FFT v13.0?

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07-09-2013
12:51 PM

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Hi, Jérôme!

Thanks for reply. As I see in
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Altera_Forum

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07-09-2013
01:58 PM

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Hi,

Yes I already simulated the FFT function under ModelSim, it worked well with the version 13.0. If I remember well, you only need the fft.vo file in ModelSim, not the fft.v (I don't know what is your fft_bb.v). Then, one thing that is often forgotten, is that you need to have the 6 cos/sin.hex files generated by the MegaWizard in the same folder as your fft.vo file. Once you are sure of these two points, if you still have trouble, I think that ModelSim should give you some warnings. Could you indicate what are they ? Could you also put a screenshot of the wave in ModelSim ?
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**# error loading design**' message. And it is clear - because fft.vo is just an 'IP Functional Simulation Model'. To test module we obviously need: 1. IP Functional Simulation Model - **fft.vo** file; 2. Module interface declaration - **fft.v** file; 3. Testbench - **fft_tb.v** file; 4. BlackBox - **fft_bb.v** file (I don't know anything about it) And to start simulation I need all of these 4 files, otherwise I get '**# error loading design**'. So, that's what I have: 1. My project window https://www.alteraforum.com/forum/attachment.php?attachmentid=7509 2. Simulation window (stopped after waiting long time) https://www.alteraforum.com/forum/attachment.php?attachmentid=7510 Have any idea about it?

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07-09-2013
02:41 PM

13 Views

Hi again, Jérôme!

If I follow your point and place in ModelSim project just one fft.vo file, simulation couldn't be started - ModelSim outputs '
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*<variation name>*_bb.v file. So I don't understand where you get this fft_bb.v file.

Altera_Forum

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07-09-2013
03:53 PM

13 Views

Hi again,

For me, I always used only the .vho file (VHDL equivalent of .vo) for the simulation and it worked. And this is what is indicated p 15 of the FFT user guide : --- Quote Start --- To simulate your design, use the IP functional simulation models generated by IP Toolbench. The IP functional simulation model is the .vo or .vho file generated as specified in “Set Up Simulation” on page 2–10. Compile the .vo or .vho file in your simulation environment to perform functional simulation of your custom variation of the MegaCore function. For more information about IP functional simulation models, refer to the Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook. --- Quote End --- And in the corresponding chapter of the Quartus II Handbook, it is indicated : --- Quote Start --- When you simulate your design, only compile the .vo or .vho for these IP cores in your simulator, rather than the corresponding HDL file, which may be encrypted to support only synthesis by the Quartus II software. --- Quote End --- So, I find strange that you need the fft.v file. Moreover, looking at Table 2-1 p 2-11 and 2-12 of the FFT user guide, which indicates the files generated by the MegaWizard, there is no
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*<variation name>*_bb.v file - it is just one of the files generated by Megacore function wizard. I didn't mess with it.

Altera_Forum

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07-09-2013
07:35 PM

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Sorry, Jérôme, but I really don't understand how to simulate the module behavior using only *.vo file. Where did you get clock? Test data? What were the output results?

If you mean that I need two files (*.vo and testbench), then, as I wrote before, I get general error message from ModelSim '# Error loading design' when trying to start simulation. And a number of small errors above it. With respect to
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Altera_Forum

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07-10-2013
09:03 AM

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Hi,

Sorry, when said that I always used only the .vho file, I meant that the fft.v file was not required, however of course there is the testbench file. --- Quote Start --- I get general error message from ModelSim '# Error loading design' when trying to start simulation. And a number of small errors above it. --- Quote End --- Look at these errors to understand the origin of the problem ! What are the first errors ? If you want, you can upload your files, and I can try to perform the simulation on my computer.
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**streaming**; Transform length: **2048**; Data input precision: **16-bit**; Twiddle precision: **16-bit**; Generate simulation mode: **verilog hdl**; Other options are left default. Then I press **generate**, wait..., then **exit** and finally I get standard folder (see in attachment). All further actions I described in my first post. Best regards, Vadim

Altera_Forum

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07-10-2013
09:39 AM

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Hi, Jérôme!

I'll be very grateful to you, if you try my module on your own. I created this FFT module with MegaFunction Plug-in manager in Quartus 2 with following parameters: I/O data flow:
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Altera_Forum

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07-19-2013
10:25 AM

13 Views

Hello, sorry for the late feedback. Did you solve your problem ?

I tried with your file, and it did not work. Then I tried to generate myself the files with the megawizard in verilog, it still did not work. Using the fft_tb.v, fft_bb.v and fft.vo files, i have the following warning when I start the simulation, I don't if this can be the origin of the problem : # ** Warning: (vsim-3009) [TSCALE] - Module 'fft' does not have a `timescale directive in effect, but previous modules do. # Region: /fft_tb/dut Then I tried to generate myself the files with the megawizard in VHDL, and here it worked (and here I effectively need only the test bench and the fft.vho files, but not the fft.vhd file). I never used verilog, so I don't know if some special things are needed compared to the VHDL. Sorry to not be able to help more. As a remark, the fft_bb file is not generated when we select vhdl, this is why I was surprised about this file (and because it is not mentioned in the documentation).
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Altera_Forum

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07-22-2013
06:06 AM

13 Views

Thanks a lot for your help, Jérôme!

No, I still didn't progressed with my problem. As there are no other comments in this thread, it seems like I need to contact Altera directly. Anyway, I wonder why nobody still didn't meet this effect...
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Altera_Forum

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07-22-2013
07:28 AM

13 Views

Yes, you can ask Altera directly.

You can post the solution once you have it, in case some people have the same problem in the future. Good luck.
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**fft.vo** and **fft_tb.v** files into it; 2. Execute following lines in transcript window (or put these to .do file): **vlib work **

**vmap work work **

** **

**vlog -reportprogress 300 -work work fft.vo **

**vlog -reportprogress 300 -work work fft_tb.v **

** **

**vlog -reportprogress 300 -work work c:/altera/13.0/quartus/eda/sim_lib/altera_lnsim.sv **

**vlog -reportprogress 300 -work work c:/altera/13.0/quartus/eda/sim_lib/220model.v **

**vlog -reportprogress 300 -work work c:/altera/13.0/quartus/eda/sim_lib/altera_mf.v **

**vlog -reportprogress 300 -work work c:/altera/13.0/quartus/eda/sim_lib/sgate.v **

** **

**vsim fft_tb **

**add wave sim:/fft_tb/*** Of course, you may need to change file pathes. Good luck!

Altera_Forum

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07-25-2013
06:45 AM

13 Views

Hi, everyone!

I contacted Altera about this problem and got quick reply. To successfully compile and simulate Verilog version of FFT megafunction in ModelSim: 1. Create project in ModelSim, append
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Altera_Forum

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10-25-2015
09:54 PM

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I tried what vadimula suggested. See imgur.com/XEF7nkT.

https://www.alteraforum.com/forum/attachment.php?attachmentid=11316 How do I verify whether the result was correct or not? --- Quote Start --- Hi, everyone! I contacted Altera about this problem and got quick reply. To successfully compile and simulate Verilog version of FFT megafunction in ModelSim: 1. Create project in ModelSim, append fft.vo and fft_tb.v files into it; 2. Execute following lines in transcript window (or put these to .do file): vlib work vmap work work vlog -reportprogress 300 -work work fft.vo vlog -reportprogress 300 -work work fft_tb.v vlog -reportprogress 300 -work work C:/Altera/13.0/quartus/eda/sim_lib/altera_lnsim.sv vlog -reportprogress 300 -work work C:/Altera/13.0/quartus/eda/sim_lib/220model.v vlog -reportprogress 300 -work work C:/Altera/13.0/quartus/eda/sim_lib/altera_mf.v vlog -reportprogress 300 -work work C:/Altera/13.0/quartus/eda/sim_lib/sgate.v vsim fft_tb add wave sim:/fft_tb/* Of course, you may need to change file pathes. Good luck! --- Quote End ---For more complete information about compiler optimizations, see our Optimization Notice.