I'm a greenhand in simulation , sinx everyone who may give me a hand in advance!I simulate the ALTGX ip with modelsim 10.1c but when i am sending the 8b/10b sequence (K28.5 D21.4 D21.5 D21.5), the output is always K28.5+ then K28.5- i don't know why . the mode i choose is basic mode ,the ALTGX signal picture and simulate pictures are as follows , can any professer tell what i was wrong In the picture I connect the tx_dataout to rx_datain so the two wave is the same , and all the input signal is included in the picture , why i always get the K28.5 THANKS again for the attention!!!
thx for answeringyes whatever input is the output is the same k28.5+ after k28.5- I havn't change version yet ! I do some other test , I try to change the ALTGX mode to strarixiv of no use I try to change the clk frequency of no use I try to use the modelsim "create wave" to generate the clk signal instead of the vhdl then the simulation can't work with "Fatal error in Process line__168 at K:/altera/15.0/quartus/eda/sim_lib/stratixiv_hssi_atoms.vhd line 172 " but what matters me most is when I download my design to the cyloneiv , it works , I can't believe it , that's good but that's not what I want! maybe I should change my modelsim version sinx
Is there something I should pay special attention to in testbench about ALTGX,the wave is up there , finding something wrong is beyond my ability now , can you give me some suggest??
I find out the problems is come frome pcs part , the output of the pcs is K28.5 whatever input is ,I change THE ALTGX to transimitter only model , only 3 port ---- clk datain and control bit,even in this simple MODE the pcs output is wrong. .