FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6669 Discussions

FFT Megacore resource usage different between software and user guide

Altera_Forum
Honored Contributor II
1,441 Views

Dear all, 

 

I post a message because I have some trouble with the resource usage of the FFT MegaCore function. I follow the procedure described in user guide (p 2-1 -> 2-7) to evaluate resource usage of the MegaCore function, and I find values differents from the user guide. Below, you have the details with two examples. 

 

The version of the software is the latest, 9.0. The target device is Stratix III. The transform length is 4096 points and the data & twiddle precision is 16 bits as specified in the user guide. 

 

I tried with the streaming architecture, using the 4 mults/2 adders complex multipliers structure as specified in the user guide. It is not specified in the user guide, but I let the implementation of multiplier by default (i.e. DSP Blocks / Logic Cells, anyway it is the one that consume the less ALUTs). 

 

With this parameter I obtain the following resource usage : 

 

ALUTs ___________________ 6077 

Memory Bits ____________ 622592 

M9K RAM Blocks _____________ 76 

DSP Block 18-bit elements ____ 48 

 

Whereas the user guide give these values (page 1-8) : 

 

ALUTs ___________________ 3732 

Memory Bits ____________ 622848 

M9K RAM Blocks _____________ 76 

18 * 18 mults _______________ 24 

 

The memory usage is approximately the same, but the number of ALUT is almost divided by two, and the number of multiplier is half the number of DSP block whereas each DSP block provides eight 18 x 18 multipliers (source : http://www.altera.com/products/devices/stratix-fpgas/stratix-iii/overview/architecture/st3-dsp.html) (http://www.altera.com/products/devices/stratix-fpgas/stratix-iii/overview/architecture/st3-dsp.html%29). 

 

I tried with other architectures, and it is the same. Here an example with burst data flow architecture, quad output engine architecture and one engine. The result is the same and the Block Throughput Cycles is also different. 

 

Me : 

 

ALUTs ___________________ 3504 

Memory Bits ____________ 229376 

M9K RAM Blocks _____________ 28 

DSP Block 18-bit elements ____ 24 

Block Throughput Cycles ___ 13421 

 

User guide (page 1-10/11) : 

 

ALUTs ___________________ 1926 

Memory Bits ____________ 229632 

M9K RAM Blocks _____________ 28 

DSP Block 18-bit elements ____ 12 

Block Throughput Cycles ____ 6157 

 

 

Can anybody tell me why I obtain values differents from the user guide ? 

 

Many thanks. 

 

Jérôme 

 

0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
751 Views

hello Jérôme, 

 

were your numbers based on the estimate at the bottom of the MegaWizard? if so try running the core through a compilation to see what the actual fit resource usage is.
0 Kudos
Altera_Forum
Honored Contributor II
751 Views

Hello, 

 

Yes, my number are those given by the MegaWizard at the bottom of the window. 

I will run the core through a compilation, and inform you on the result. But it would be strange that the estimation be so far from the actual values. 

 

Thanks.
0 Kudos
Altera_Forum
Honored Contributor II
751 Views

i would say there may be a bug in the MegaWizard and the ALUTs and MULTs are off by a factor of 2. 

 

i did a 4096-point 16-bit streaming FFT on Stratix III with all other settings as default. MULTs are estimated at 48 but are actually 24 after the mapper. LUTs are estimated at 6077 but are 3770 after the mapper. 

 

i know the resource estimator is not supposed to be 100% accurate but there is probably a bug in the math somewhere.
0 Kudos
Altera_Forum
Honored Contributor II
751 Views

Indeed, I test also and the values after compilation correspond to those given in the user guide. It must be propably a bug in the MegaWizard, as you said. 

 

Many thanks.
0 Kudos
Altera_Forum
Honored Contributor II
751 Views

I am working on FFT Mega core IP and I want to give the generated file 64 points and get the output using the Altera board not a simulation. 

 

I build a top level file to pass the inputs but there is no outputs. 

 

Can any one help, please???? 

 

Thanks
0 Kudos
Reply