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Altera_Forum
Honored Contributor I
995 Views

FFT output spectrum generation

Hi all,  

 

I just have a simple question regarding to FFT output. I understand that the output of the real and imag signal have signed value, and these has to be divided by exponent value in order to get the real value. The question I have is how should I get the spectrum more specifically range and the magnitude of the specific frequency! I am new to FFT core. I am looking forward to your reply! Thank you very much! 

 

Best,
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Altera_Forum
Honored Contributor I
11 Views

exponent scaling is for both real and imaginary output separately. Power is Re^2+Im^2 (without averaging) per bin of fft.  

frequency of a bin = bin_index * sampling rate/fft resolution (for indices 0 - fft resolution/2-1), thereafter it is negative (mirror) = -(fft_resolution - bin_index) * sampling rate/fft resolution
Altera_Forum
Honored Contributor I
11 Views

Thank you very much for your reply! And I have an additional question regarding to the FFT IP core output data streaming. From the specs, I know that the output is a sourcing data. Does the data have to connect with Avalon ST? Can I use normal wire connection to make the data passing to the next block? And additionally, in order to get the real output of the FFT result, a shifting of original data should be performed based on exponent, right? In order to shifting the original data, more than one cycle will be needed. However, the output of the data is a streaming data bus, which keeps streaming data as long as the FFT transform is done. Is there a way to control the fft ip core output? If not, how to achieve controlling the data streaming in order to perform the shifting bits without messing with the timing constraint? Thank you very much! I am looking forward to your reply!

Altera_Forum
Honored Contributor I
11 Views

 

--- Quote Start ---  

Thank you very much for your reply! And I have an additional question regarding to the FFT IP core output data streaming. From the specs, I know that the output is a sourcing data. Does the data have to connect with Avalon ST? Can I use normal wire connection to make the data passing to the next block? And additionally, in order to get the real output of the FFT result, a shifting of original data should be performed based on exponent, right? In order to shifting the original data, more than one cycle will be needed. However, the output of the data is a streaming data bus, which keeps streaming data as long as the FFT transform is done. Is there a way to control the fft ip core output? If not, how to achieve controlling the data streaming in order to perform the shifting bits without messing with the timing constraint? Thank you very much! I am looking forward to your reply! 

--- Quote End ---  

 

 

you can connect fft output to any block provided you pass source vld. 

You don't need clock cycles and you don't need shift, just put zeros in LSBs or remove LSBs as required in one go.
Altera_Forum
Honored Contributor I
11 Views

Hi, 

 

I understand your point. But the when you actually coding, you can't just do a pack based on a fixed number, right? because the exponent value is different. So, are you suggesting to write a case statement to hard code the logic? If not, could you please give me some hints on this, because the only other way I figure out to do this is through a shifting register. And besides this, I still have one question. How to control the FFT output? By that, I mean way to control FFT to start streaming or stop streaming at our wish. Thank you very much!
Altera_Forum
Honored Contributor I
11 Views

 

--- Quote Start ---  

Hi, 

 

I understand your point. But the when you actually coding, you can't just do a pack based on a fixed number, right? because the exponent value is different. So, are you suggesting to write a case statement to hard code the logic? If not, could you please give me some hints on this, because the only other way I figure out to do this is through a shifting register. Thank you very much! 

--- Quote End ---  

 

 

yes you put the logic but no need to wait, e.g. 

case exponent is when -3 => re_sc <= re(28 downto 0) & "000"; im_sc <= im(28 downto 0) & "000"; when -4 => re_sc <= re(27 downto 0) & "0000"; im_sc <= im(27 downto 0) & "0000";
Altera_Forum
Honored Contributor I
11 Views

Hi, 

 

Thank you very much for your reply! I made an edition on my original post. I have got one more question regarding to FFT output. is there a way to control the FFT output data at our wish? Thank you very much! 

 

best, 

 

Jingyuan Ma
Altera_Forum
Honored Contributor I
11 Views

 

--- Quote Start ---  

Hi, 

 

Thank you very much for your reply! I made an edition on my original post. I have got one more question regarding to FFT output. is there a way to control the FFT output data at our wish? Thank you very much! 

 

best, 

 

Jingyuan Ma 

--- Quote End ---  

 

 

If sink valid is halted(low) then I assume it supports fft hanging otherwise it is streaming out. Then source vld should go low as well. You can also add fifos at output if it helps your requirements