FIFO Intel FPGA IP (DCFIFO) with clock that is not continuous

[emery]

With the DCFIFO connected directly to FPGA device pins where the external device provides a Master Serial Peripheral Interface (SPI).  The SPI clock is only present when clocking in/out data. 

Therefore will the FIFO Intel FPGA IP still be happy when one of its clocks is not continuous?

(aclr input will not be used and the flags will be ignored on the side where the clock is not continuous)

(On the other side would be the FPGA fabric logic that would have a continuous clock).

Thanks

[Ash_R_Intel · Accepted solution]

Hi,

Consider that you have a DCFIFO which has continuous rdclk but wrclk comes in only with the data, i.e. one clock per data.

The problem with this type of write clocking is that you need at least one extra clock to read the last data. Reason is this setting for DCFIFO:

Minimal setting for unsynchronized clocks

This option uses two synchronization stages with good metastability protection. It uses the medium size and provides good fMAX.

This needs an extra clock to compensate for the two synchronization stage.

Reference: https://www.intel.com/content/www/us/en/programmable/documentation/eis1414462767872.html?wapkw=FIFO%20Intel%20FPGA%20IP

Similar thing if the FIFO has continuous wrclk but sparse rdclk.

To understand it better, you may run simulations before implementing it on board.

Regards

[Ash_R_Intel]

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