FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6018 Discussions

FIFO Intel FPGA IP (DCFIFO) with clock that is not continuous

emery
Novice
249 Views

With the DCFIFO connected directly to FPGA device pins where the external device provides a Master Serial Peripheral Interface (SPI).  The SPI clock is only present when clocking in/out data. 

Therefore will the FIFO Intel FPGA IP still be happy when one of its clocks is not continuous?

 

(aclr input will not be used and the flags will be ignored on the side where the clock is not continuous)

(On the other side would be the FPGA fabric logic that would have a continuous clock).

 

Thanks

 

 

0 Kudos
1 Solution
Ash_R_Intel
Employee
225 Views

Hi,

Consider that you have a DCFIFO which has continuous rdclk but wrclk comes in only with the data, i.e. one clock per data.

The problem with this type of write clocking is that you need at least one extra clock to read the last data. Reason is this setting for DCFIFO:

Minimal setting for unsynchronized clocksThis option uses two synchronization stages with good metastability protection. It uses the medium size and provides good fMAX.

This needs an extra clock to compensate for the two synchronization stage.

Reference: https://www.intel.com/content/www/us/en/programmable/documentation/eis1414462767872.html?wapkw=FIFO%...


Similar thing if the FIFO has continuous wrclk but sparse rdclk.

To understand it better, you may run simulations before implementing it on board.


Regards


View solution in original post

2 Replies
Ash_R_Intel
Employee
226 Views

Hi,

Consider that you have a DCFIFO which has continuous rdclk but wrclk comes in only with the data, i.e. one clock per data.

The problem with this type of write clocking is that you need at least one extra clock to read the last data. Reason is this setting for DCFIFO:

Minimal setting for unsynchronized clocksThis option uses two synchronization stages with good metastability protection. It uses the medium size and provides good fMAX.

This needs an extra clock to compensate for the two synchronization stage.

Reference: https://www.intel.com/content/www/us/en/programmable/documentation/eis1414462767872.html?wapkw=FIFO%...


Similar thing if the FIFO has continuous wrclk but sparse rdclk.

To understand it better, you may run simulations before implementing it on board.


Regards


Ash_R_Intel
Employee
107 Views

This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Reply