First, apologies if I have done this wrong. This is my first post ever to a forum.
I am a bit of a beginner when it comes to DSP on an FPGA. My boss has given me a code already done by an outside company and asked if I could add a filter to the end of it. I've tried a few different things but it always comes back to needing an EOP and SOP input/output signals in order to keep the timing right with the rest of the program.
Nothing I have done generates those signals for me. Do I need to manually add these signals to the instantiation templates generated, or is there something super simple I am missing.
Thanks for any nudge in the right direction!
A few key components of this filter:
Accepts 4 channels, 16 bit wide inputs coming in at 5msps.
If I need to add more info I can.
As I understand it, you have some inquiries related to the SOP and EOP for the FIR II. For your information, user would need to specify the SOP and EOP by controlling the ast_sink_sop and ast_sink_eop input signals. You may refer to the FIR II IP user guide for further details. Alternatively, you may also generate simulation example from the FIR II IP and refer to the signal activities.
Please let me know if there is any concern. Thank you.