FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

FIR IP

ElizabethJaison
Beginner
158 Views

Hi,
I was simulating a 35 tap fractional filter operating at 150MHz clock implemented using intel FIR IP.
The input sampling rate is 150msps and output sampling rate is 100msps (interpolation factor:2, decimation factor:3).
So the ip gives 2 valid data output in 3 clock cycles as represented in case 1 in the attached excel sheet(refer SRC_DOWN23_FIR_IP_configurations and timing_diagram.xlsx)
But is there any chance of getting output data as represented in case2 in SRC_DOWN23_FIR_IP_configurations and timing_diagram.xlsx ?

 

Thanking you in advance.

Elizabeth

0 Kudos
0 Replies
Reply