FIR filter

Altera_Forum · ‎04-16-2009

Hi,

I'm using the FIR filter compiler of the megawizard to compile 2 bandpass filters. It all goes well 'till I use them in a toplevel. Somehow I can't seem to find my mistake.

The filters use each a different clock (60 MHz PLL clock and a 229 Hz clock) as sample frequencies.

When compiling I get warnings: "No clock transition on .... register" these registers are located in the encrypted files of the FIR Filters.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Toplevel is
port(
 SYSTEM_CLOCK : in std_logic; --System clock is 100MHz
 reset   : in std_logic;
 indata   : in std_logic_vector(7 downto 0);
 outdataV  : out std_logic_vector(7 downto 0);
 outdataH  : out std_logic_vector(7 downto 0)
);
end Toplevel;
architecture behav of Toplevel is
 component VsyncFilter
  port( 
  clk : IN STD_LOGIC;
  reset_n : IN STD_LOGIC;
  ast_sink_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
  ast_sink_valid : IN STD_LOGIC;
  ast_source_ready : IN STD_LOGIC;
  ast_sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
  ast_source_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
  ast_sink_ready : OUT STD_LOGIC;
  ast_source_valid : OUT STD_LOGIC;
  ast_source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
  );
 end component;
 
 component HsyncFilter
  port ( 
  clk : IN STD_LOGIC;
  reset_n : IN STD_LOGIC;
  ast_sink_data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
  ast_sink_valid : IN STD_LOGIC;
  ast_source_ready : IN STD_LOGIC;
  ast_sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
  ast_source_data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
  ast_sink_ready : OUT STD_LOGIC;
  ast_source_valid : OUT STD_LOGIC;
  ast_source_error : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
  );
 end component;
 
 component PLL
  port(
   areset   : in std_logic;
   inclk0   : in std_logic;
   pllena   : in std_logic;
   c0       : out std_logic;
   locked   : out std_logic   
  );
 end component;
 
 signal one  : std_logic := '1';
 signal Clk : std_logic; -- clock 60 Mhz
 signal noerror : std_logic_vector(1 downto 0) := "00";
 signal locked : std_logic;
 signal ctr : std_logic_vector(18 downto 0);
 signal Clk229 : std_logic;
 
begin
  -- transform 60MHz clock to 229 Hz by adding a counter 
 
  counter : process(Clk, reset)
  begin
  if reset = '1' then
   ctr <= (others => '0');
  elsif rising_edge(Clk) then
   ctr <= ctr + 1;
  end if;  
  end process counter;
 
  Clk229 <= ctr(18);
  Clk229out <= Clk229;
  U1 : VsyncFilter
 port map (
  clk => Clk229,
  reset_n => NOT reset,
  ast_sink_data => indata,
  ast_sink_valid => one,
  ast_source_ready => one,
  ast_sink_error => noerror,
  ast_source_data => outdataV
 );   
 
  U2 : HsyncFilter
 port map (
  clk => Clk,
  reset_n => NOT reset,
  ast_sink_data => indata,
  ast_sink_valid => one,
  ast_source_ready => one,
  ast_sink_error => noerror,
  ast_source_data => outdataH
 );
 
  U3 : PLL
 port map (
  areset   => reset,
  inclk0   => SYSTEM_CLOCK,
  pllena   => one,
  c0       => Clk,
  locked   => locked 
 );
 
end behav;

thanks in advance,

Steven

Altera_Forum · ‎04-16-2009

Hi,

Have you connected system_clock!!!

what is driving clk?

edit:

sorry you have...

Altera_Forum · ‎04-16-2009

You must set one as '1' in the architecture as assignment:

begin

.....

one <= '1';

because initialisation is ignored by synthesis tool except for memory at least