DDR2 SODIMM Verification + probing solutions

[Altera_Forum]

Hi all, 

I hope I don't get shouted at for posting a verification thread on this forum - sorry if there's a more appropriate forum but I thought some of you here may have been through this already.    Do any of you have any experience of using Tek logic analysers and Nexus interposers? As they say probing at the SODIMM fingers with an interposer is not the ideal position to probe.  I had Mentor's HyperLynx hired for a while to check out our design (pre-layout) - a quick peek at the signals at the SODIMM fingers showed some ugly signals at this point while everything is good ar the DRAM balls where it's supposed to be.    Any feedback greatly appreciated as I need to make some decisions very soon about what proing solution to go with.   Stephen.

[Altera_Forum]

I'm not understanding. Is you're board fabricated and not working or are you designing a board now? 

 Jake

[Altera_Forum]

I'm designing now - but for validation of protocol, timings etc on real hardware I want to use our logic analyser - to do this I need to make a physical connection between the logic analyser probes and the DDR2 SODIMM. See NexusTechnology products at www.busboards.com/ (http://www.busboards.com/) 

 I wondered if anyone on this forus has any experience of using either an Interposer or a Nex-Vue product?   Stephen

[Altera_Forum]

Okay well I'm not going to claim to be an authority on this. At one time I worked for a very large DRAM manufacturer. I designed Flash, DDR, and DDR2 memory test equipment. 

 First you need to ask yourself what it is you are trying to analyze.  1 - Are you designing your own memory controller and need to analyze gross timing of your control / data signals? A logic analyzer is appropriate and useful in this case and I wouldn't hesitate suggesting that you buy the interposer.  2 - Are you just anticipating problems in your PCB layout and want to be able to analyze them when the memory doesn't work? A logic analyzer is not as useful here. It may help tell you if you've got an open or short somewhere. It might reveal if you've made some dramatic mistake (like making one DQ trace in a group far too long or short compared to the others). But if you are trying to view the signal integrity of the signals, this is not going to help.  . If you measure the signals anywhere except at the destination pins (FPGA or memory pins depending on who's driving), the signal is not going to look good. I'm sure you understand why this is the case.   If you need to do some signal integrity checking, it's best to probe the module at the via that connects to the ball in question. We would often take a DIMM or SODIMM and rip some of the parts off it so we could probe at the best places. Or we would solder little test pins to the module so we could connect an oscope or logic analyzer to them.  Again, just my opinion. Maybe somebody else will have something better.  Jake

[Altera_Forum]

Thanks Jake. 

 Just to put things in context - this is our very first DDR2 design, we want to ensure that the IP controller is working OK, that we'ce configured it properly, that the DDR2 is initialised Ok and mode registers loaded with correct data, we're not violating the protocol regarding timings between issuing commands, refreshes etc.   I know for SI work I'll need to get the scope and active probes out but for the type of stuff described the analyser is a good tool. I don't want to blow our budget on an interposer which probes at the SODIMM fingers where SI is not great (Nexus don't guarentee that the analyser will be able to capture properly here) whereas the Nex-Vu product probes at the DRAMM balls wher e our simulations show acceptable SI.    Our design will be populated with two different densities of SODIMM so ideally I want to verify both modules - one interposer would do the job but it would take two Nex-Vue boards (at many $)   Stephen

[Altera_Forum]

Are you using the Altera DDR2 controller? 

 Jake

[Altera_Forum]

And what device family are you targetting?

[Altera_Forum]

Yes Jake - the HP Memory Controller. 

 Stephen

[Altera_Forum]

Stratix III

[Altera_Forum]

I would say rest assured the Altera HP memory controller works. I have complete confidence in it as I've used it in several Stratix II designs now. Altera's memory controllers are really very good and very easy to use. 

 The best thing you can do is what you're already doing: 1 - Simulate using Hyperlynx. This is priceless and it's great that you've had access to the tool to do it. 2 - Constrain, constrain, constrain the interface on the PCB. Even if you spend an extra 3 days in layout doing trace matching it's worth it. Follow the guidelines provided by the memory manufacturers (primarily Micron). Don't hesitate to overconstrain a bit.  If you are going to have any problems with your memory interface it will be: 1 - A poor layout. 2 - A schematic mistake (didn't connect something properly).  My most recent board has two DDR2 SODIMMs on it. My current company does not have the luxury of Hyperlynx. We don't even have a logic analyzer and there is not a scope in this entire building with an active probe that can measure DDR2 signals. All we could do is follow the rules. Both of those DIMMS fired up first time at 333MHz (limit for Stratix II) with the HP controller and ran without a single issue. So far I've never even had to look at the signals. Follow good PCB design rules and you should be just fine.  Jake

[Altera_Forum]

Thanks again Jake. 

 Regarding HyperLynx - we didn't budget for this initially - but you can hire it by the month which we did and it was very worthwhile. Check out your Mentor rep if the offer that where you are.   The main issue in layout we're facing is trying to distribute the power nets around the FPGA which ends up splitting planes. We're striving not to have any high-speed DDR2 nets crossing over any of these splits as per memory and FPGA vendor's app. notes. Any feedback on this particular issue would be good.   Stephen

[Altera_Forum]

Yes do not run the DDR2 traces over a plane split. You may have to increase your layer count to make this happen. 

 Jake

[Altera_Forum]

One more thing from your last post Jake - if you don't have access to a fairly fast scope, Logic analyser etc how do you verify/gain confidence that everything's as it should be and you have some margin? 

 Will your design ship in quantity?   Stephen.

[Altera_Forum]

Jake - would you be willing to pm me with your stack-up?? My design is a two SODIMM design also. 

 Just thought to ask. thanks again for your replies - very helpful. Stephen

[Altera_Forum]

We do have a few scopes that have adequate speed, but no probes to go with them. I know you're thinking that doesn't make any sense. We design video broadcast equipment so we can do 95% of what we need to without a scope probe. 

 Our primary concern on the board are multi-gigabit serial links so the memory becomes somewhat of an afterthought.  Our quantities may be fairly low compared to yours. However, we run all of our assembled boards through a complete memory test at the assembly house so we have a high level of confidence they will work properly.  I may be able to send you the stackup. What is your board's layer count? What dielectric are you planning on using?  Jake

[Altera_Forum]

We're in the process of completeing it right now - its 14 layer in FR4 

 Stephen

[Altera_Forum]

I've sent you a PM. 

 Jake

[Altera_Forum]

I think I've replied - my sent number is still 0 - did it arrive Jake - pm me back if my response is insufficientlet. 

 Stephen