FIR: getting coef_ld to show up in DSP Builder

[Altera_Forum]

I lost many sleepless nights again trying to get FIR coefficient reload to simulate properly in DSP Builder. I thought I would share my experience with everyone. Hopefully I can save you some time. 

 My FIR setting: - 6.1 - MCV structure - 1 cycle/output - pipeline level 3 - coefficient and data are both stored in LE - coefficient scaling is turned off - forced non-symmetry - original coefficient [1 0 0]   I understand that with this configuration, coef_ld is actually missing. The errata talked about how I could heck the generated HDL files to get this port to show. However, there was one problem: the user guide said that coef_ld is an input (when it is supposed to be an output!)    Also one more thing that the errata or the user guide did not talk about: if you try to overwrite your coefficients that are stored in LE, the new values will disappear after reset.   Furthermore, it is almost impossible to get coef_ld to show up in DSP Builder. To get the newly added port to show up in DSP Builder, you have to regenerate the megacore. However, when you regenerate your megacore, you lose coef_ld again. It's a chicken-and-egg problem. That CAUSED me a lot of sleepless nights.   I finally found a work-around to that problem: - Generate a quartus project. - Instantiate the FIR core as the top level module for that project. - Heck the VHDL/Verilog file to get coef_ld to show up. - Run "Start Analysis and Elaborate" on that project. - Once that's done, go back to your DSP Builder design and import that project via HDL import. Voila! You can now simulate your FIR in DSP Builder.   I ran into a second problem when I tried to run RTL simulation of my DSP Bulider design in ModelSim. Typically SignalCompiler generates simulation files, input stimuli and ModelSim tcl script. However, in this case, the tcl script failed for me (I think this is because I imported a Quartus project, which is hidden to SignalCompiler). Long story short, the steps that it took to get it to work are outlined below: 

• Create a Quartus project of the DSP Builder design using signal Compile (step 1 – 3 => maybe 1 and 2 are good enough…). 
• Open up that project:   --- Quote Start ---   
• analyze & elaborate 
• analyze & synthesis 
• run EDA tool to create functional netlist  --- Quote End ---   
• Open up ModelSim and create a new project. 
• Add <new DSP Builder Project>.vho and tb_<DSP Builder project>.vhd (Signal Compiler generated this for you) to the project. 
• Compile both files. 
• Go to the main GUI window and type the following (essentially copying and pasting some of the original tcl scripts):

   --- Quote Start ---  # setting some timing parameters set SimTime 12090 set TimeResolution 1ps # adding signals to the wave add wave -label clock /tb_myReloadableTest/clock add wave -label "global reset (sclrp)" /tb_myReloadableTest/SystemReset add wave /tb_myReloadableTest/reset add wave -radix dec /tb_myReloadableTest/ast_sink_data add wave /tb_myReloadableTest/ast_sink_eop add wave /tb_myReloadableTest/ast_sink_ready add wave /tb_myReloadableTest/ast_sink_sop add wave /tb_myReloadableTest/ast_sink_valid add wave -radix dec /tb_myReloadableTest/ast_source_channel add wave -radix dec /tb_myReloadableTest/ast_source_data add wave /tb_myReloadableTest/ast_source_eop add wave -radix dec /tb_myReloadableTest/ast_source_error add wave /tb_myReloadableTest/ast_source_sop add wave /tb_myReloadableTest/ast_source_valid add wave -radix dec /tb_myReloadableTest/coef_in add wave /tb_myReloadableTest/coef_ld add wave /tb_myReloadableTest/coef_we # run simulation: run $SimTime ns  --- Quote End ---   Voila! We have our modelsim simulation!   P.S. I have included my DSP Builder design for those who are interested.