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5918 Discussions

Wishful feature for DSP Builder

Altera_Forum
Honored Contributor II
1,172 Views

In most of my design (in RTL), I used the “generate” statement so that the IP can be parameterized under different conditions/parameter ( like “generate if” in Verilog), or for a number of instantiations (like “generate for 1 to n”). This feature is quite necessary if we want to build generic/reusable IP with DSPbuilder. This “generate” feature also demands the support of multiple (at least two) dimensional array with parameterizable array index bounds. It would be great if DSPbuilder can follow the “generate” capability of VHDL or Verilog.

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4 Replies
Altera_Forum
Honored Contributor II
342 Views

Wish List: 

 

1. Certain status/message to indicate if the current simulation is native Simulink simulation or HIL simulation. There was a case that I had problem with HIL, but hitting the simulink simulation button would still trigger native simulink simulation. I just can’t tell if the undergoing simulations is native or HIL. 

 

2. It would be great if user doesn’t need to compile twice to use HIL. In theory, the tool can be made to compile just once, right? Compiling twice easily offset the benefit of faster simulation time. 

 

3. Allow signal tap or scope/display in the design.
Altera_Forum
Honored Contributor II
342 Views

Hi Wronghorizon, 

 

1. When do the simulation, the output from the HIL block is the HIL simulation result. Other that this, all of the will be the simulink result. It's not too difficult to identify 

 

2. It could be that the HIL test is not the same device as the DSPbuilder project. Thus the customer might lose the chance to configure, if only compile it once. 

 

3. Signal Tap, Scope, and Display are all allowed in the design already. 

 

Butonlyif
Altera_Forum
Honored Contributor II
342 Views

I agree with 1. 

For 3, it's definitely a problem. I wanted to have a way of using signal tap, scope and display to probe inside the HIL project. Is that what you mean?
Altera_Forum
Honored Contributor II
342 Views

The test of HIL and SignalTAP are completely different model.  

It is not so necessary to use the Singaltap in the HIL Because you can just do the partial of the design into HIL project. You don't have to put the whole project into the design. 

 

And also, you can put the signaltap and HIL into the same model and run them seperatedly. Since the HIL is only the simulation, too. It's might not be the very good idea to embed the SignalTap into the HIL.
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