FPGA IP catalog name: LDPC Decoder (WiMedia 1.5)
After I was able to run a simulation using the attached .tcl, There seems to be no indication as to whether the LDPC was able to decipher the information bits or how many iterations it took.
Just would like to check with you if you are performing Modelsim simulation with the example design generated by the LDPC IP? Based on my understanding, after you generate the example design, you should be able to see data to be fed into the decoder. You can then perform manual decoding and then compare with decoder output.