FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5950 Discussions

FPGA IP catalog name: LDPC Decoder (WiMedia 1.5) After I was able to run a simulation using the attached .tcl, There seems to be no indication as to whether the LDPC was able to decipher the information bits or how many iterations it took. Avi

AVahd
Beginner
719 Views

Arria II GX

0 Kudos
1 Reply
CheePin_C_Intel
Employee
112 Views
Hi Avi, Just would like to check with you if you are performing Modelsim simulation with the example design generated by the LDPC IP? Based on my understanding, after you generate the example design, you should be able to see data to be fed into the decoder. You can then perform manual decoding and then compare with decoder output.
Reply