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Fast Clock of ALTLVDS_rx megafunction with external PLL

Altera_Forum
Honored Contributor II
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Hello, guys. I have a simple question.  

I'm creating ALTLVDS_rx megafunction with external pll on Cyclone V. Which high speed clock rate (rx_inclock) should I use? 

Support says that C0 (Fast Clock): Freq = data rate, C1: Freq = data rate / serialization factor. 

But "LVDS SERDES Receiver IP Core User Guide", page 3, tells us that "The Cyclone series uses DDIO register as part of the SERDES interface. Because data is clocked on both the rising edge and falling edge, the clock frequency must be half the the data rate." ... so Table 3 : "Fast Clock = Data Rate / 2, Slow Clock (outclock) = Data Rate / seralzaion factor".
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