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Fitter cannot place periphery component due to conflicts with existing constraints.

SKuma36
Beginner
996 Views

Hi,

 

I'm targeting a third party Soft PCIe Endpoint IP core to Arria10 FPGA on Arria 10 GX Transceiver Signal Integrity Development kit.

 

During Fitter stage, I get the below errors.

 

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_PMA_TX_CGB(s)). 

Error (175001): The Fitter cannot place 1 HSSI_PMA_TX_CGB, which is within Arria 10 Transceiver Native PHY a10_x4_gen2_phy_altera_xcvr_native_a10_161_6277cpa.

Error (16234): No legal location could be found out of 71 considered location(s). 

Error (175006): Could not find path between the HSSI_PMA_TX_CGB and destination HSSI_PMA_TX_BUF

Error (175022): The HSSI_PMA_TX_CGB could not be placed in any location to satisfy its connectivity requirements

Any idea how to overcome this? Are these errors related to Transceiver location constraints? Kindly suggest.

 

thanks,

sunil

0 Kudos
2 Replies
a_x_h_75
New Contributor III
199 Views

Yes, this will be related to the location constraints. You could try removing all relevant constraints and seeing where Quartus places the phy. It's likely to be that it can't use a particular clock input pin with that transceiver.

 

Given that you suggest this is 3rd party IP, I also suggest you contact the vendor for help.

 

Cheers,

Alex

Nathan_R_Intel
Employee
199 Views
Hie Sunil, Yes this seems related to transceiver location constraints. Please check if you are following the PCIe channel placement guideline as described in Section 4.4. in Arria 10 PCIe user guide. The link to user guide is below: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf Regards, Nathan
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