Floating Point Multiplier latency???

[Altera_Forum]

Hello,  

 i have instantiated and synthesized an ALTFP_MULT in QuartusII with double precision and 5 output latency.   I have extracted the post-synthesis netlist and successfully simulated in Modelsim. Now.. my problem is that the latency of 5 doesn't match with the simulation results!   Actually i get my results 1 cycle earlier, eg. after 4 cycles. I tried simulating a multiplier of 10 latency as well and i was getting the same... result after 9 clock cycles!   What is wrong? Are the altera specifications wrong? Have i misinterpreted the term output latency?   One IMPORTANT question pls: Is it possible for the multiplier to produce results at different latencies? For example for small numbers in 4 clock cycles for bigger numbers in 5 clock cycles etc   thx

[Altera_Forum]

Looks like 5 clock cyles to me. Just counting the rising edges in your simulation, I see 5. The output comes out exactly in line with the 5th rising edge because you're doing an RTL simulation, but in essence think that it occurs "after" that edge, as nothing can use it until the next rising edge. So it occurs through 5 edges(imagine 5 registers in a row), and each register sends its data out immediately. If you go to a timing simulation(which I generally don't recommend), the data will come out some finite time after this edge.

[Altera_Forum]

Thank you Rysc! My problem was that I was misinterpreting the term output latency. 

 In fact it was the clock periods that I have been counting and not the edges that actually triger the registers.   So, for this design the combinational stages are 4, and the registers are 5. It takes 5 clock ticks to get a result.   Thanks for your time, +1 rep from me