Timing Violation for legacy DDR2 Controller

[Altera_Forum]

Hi There, 

 I generated DDR2 SDRAM controller using mega wizard for memory frequency of 125 MHz and data width of 8. Timing analysis is failing because of violation in read data synchronization path. What can be the solution to suppress to these errors  Please respond  Regards, Harsh Bandil

[Altera_Forum]

Did you run the TCL script generated by the megacore? This performs placement of various registers in the data path. 

 Jake

[Altera_Forum]

But from the controller document, I can see "When we compile a project after generating or editing and re-generating the variation, the auto_add_ddr_constraints.tcl script automatically calls the constraints script specific to each instance of the controller in the design". So I did not feel any necessity of running the script after generating the variation.  

 The input frequency for the PLL is 80 MHz. So I edit the pll parameters and did the compilation. There was no warning. But when I edited the pin locations as per the board we have. It failed timing analysis. So I would like to know, what else steps are to be taken after we edit the pin assignments as per our requirement.  For your reference, I am using the following pin assignment for the Stratix II GX device   PPC2_DDRACLK0 AJ11  PPC2_DDRACLK1 AL11  PPC2_DDRAADD0 AJ12  PPC2_DDRAADD10 AL12 PPC2_DDRAADD11 AG14 PPC2_DDRAADD12 AC13 PPC2_DDRAADD13 AD13 PPC2_DDRAADD2 AF11  PPC2_DDRAADD3 AH11  PPC2_DDRAADD4 AM12  PPC2_DDRAADD5 AG13  PPC2_DDRAADD6 AP13  PPC2_DDRAADD7 AL14  PPC2_DDRAADD8 AH12  PPC2_DDRAADD9 AE11 PPC2_DDRABA0 AM11  PPC2_DDRABA1 AG11  PPC2_DDRACONTROLT0 AF10 WE# O  PPC2_DDRACONTROLT1 AG10 RAS#  PPC2_DDRACONTROLT2 AE9 CAS# O  PPC2_DDRACONTROLT3 AP7 CS# O  PPC2_DDRACONTROLT4 AM7 DQS# O  PPC2_DDRACONTROLT5 AL7 DQS O  PPC2_DDRACONTROLT6 AL8 RDQS O    PPC2_DDRADATAT0 AG8 Data Pin  PPC2_DDRADATAT1 AN8 Data Pin  PPC2_DDRADATAT2 AM8 Data Pin  PPC2_DDRADATAT3 AJ8 Data Pin  PPC2_DDRADATAT4 AK8 Data Pin  PPC2_DDRADATAT5 AJ7 Data Pin  PPC2_DDRADATAT6 AP8 Data Pin PPC2_DDRADATAT7 AH7 Data Pin

[Altera_Forum]

Hi, 

in the wizard there is a section called "constraint"! Do you edit this section? In your installation directory "C:\Altera.." is there an example where the ddr2 sdram controller is used? You can copy the setting from the example! I fixed my problem in this way!  Bye

[Altera_Forum]

I did not edit the "constraints" section in the Megawizard. I am not able to find the example where DDR2 SDRAM controller is used. Can you please tell me the exact path.

[Altera_Forum]

Hi, 

I have several examples of different systems in this directory:  C:\altera\kits\StratixII_GX_DSP_Kit-v6.0.1  Inside this folder shold be another folder named "examples", here you could find a system that use ddr2 sdram controller.  If there isn't tell me what sdram controller you use! I use this: "DDR2 SDRAM Controller MegaCore Function - Altera Corporation" If is the same I give you my settings.  Bye Luca

[Altera_Forum]

Thanks Luca for quick reply. I think I am using old version Quartus II 7.1. I dont see any directory like this there. Yes I am using the same legacy DDR2 controller. There are two controllers for DDR2 - one is high performance and another is legacy(no calibration). I am using the normal one. Please Share the settings with me. 

 Regards, Harsh Bandil

[Altera_Forum]

Ok.. 

I use Cyclone II DSP but I think that the settings are equals! I attach all my settings! I hope that this is useful for you.  Luca

[Altera_Forum]

All settings are same, except constraints, and I believe for different target device, it has to vary. The constraint setting page for StratixIIGX1152 is different from what you sent to me.

[Altera_Forum]

Hi There, 

 The compilation is failing for the pin assignments as shown in the above posts. Pls suggest how we can compile the design for this pin assignment.  Regards, Harsh Bandil