How variable? How fast does the frequency change?If your external clock changes over a very small range of frequencies, then you might be able to leave the PLL with a wide bandwidth loop setting. Altera PLLs are reprogrammable using the ALTPLL_RECONFIG megafunction. So long as you have an estimate of the input frequency, you can determine the appropriate PLL programming parameters (mainly that you keep the VCO within is operating frequency range). You can estimate the external frequency using another oscillator, eg., an on-board clock. That on-board clock can be used to generate an enable pulse of say 100ms. That enable pulse would be synchronized to your external clock and used to enable a counter in that clock domain, and then synchronize that back into the original clock domain as a handshake. At the end of the 100ms count, you can wait for the handshake to deassert, read the counter count value, and estimate the external clock frequency. You can average these estimates if needed. Cheers, Dave
If you review the Quartus compilation port, you'll notice that a lock frequency range is reported for every PLL under Fitter/Resource Section/PLL Summary. It's ususally in a 1:2 range, mostly below the nominal reference frequency. For application needing a larger range, e.g. digital video interfaces, reconfiguration based on a frequency measurement should be considered as already suggested.