I would like to test the FFT IP.
As such I tried to use the example that is generated with the IP parameter editor (quartus 17.1), but it generates only stuff in verilog while I need vhdl. Moreover, everything is automated with a script (compilation) and as such I don't know how to organize the files in my own project in modelsim.
So my question is: after having generated the IP with quartus, what files are required to be imported in ModelSim in order to be able to launch a simulation of the block?
- While Configuring parameters of FFT IP use "Generate HDL.." tab & choose VHDL under Synthesis & Simulation.
- Check output Directory path.
- Then click on "Generate"
- Use that generated .vhd file under Synthesis Directory as a design under test(DUT) in ModelSim & write a test bench for simulation if you don`t want to simulate it using TCL script.
5. If you want use Automated test bench then use NativeLink.
Let me know if this has helped resolve the issue you are facing or if you need any further assistance.
Sadly is not working.
I imported the file as you said and passed the input as specified in the manual, but the block doesn't do anything. Not even error on the error line.
EDIT: I am using variable streaming with fixed point.