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Fundamental question about Jesd204B, Lanes VS ADCs

dsun01
New Contributor III
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Dear Intel Support/Expert

I have a fundamental question while I am working on Jesd204B IP. 

I need to use Arria 10 GX develop board, to implement a 64 channels ultrasound system. 

the basic idea is. use 4 TI AFE58JD48, each one is configured to 4 lanes, 16 ADC, 16 bits resolution, so LMF = 4X16X8.  assume use 6144M lane speed. and 76.8M pll/CDR reference clock frequency. 

per my understanding, for 4 lanes support 16 ADC X 16 Bits = 256 bits, each lane(frame) corresponds to 64 bits.  TI AFE58JD48 has an 80X mode. which means sample clock = lane rate / 80, in this case, 76.8M sample clock. 

but in Intel Jesd204B IP, each lane fixed to 32bits(frame). which means it only support 40X mode. which means sample clock = lane rete / 32(if ignore the 8b/10b). 

I assume that if I set the TI AFE58JD48 to 80X mode( LMF = 4X16X8, each frame has 8 octets). set Intel IP core to X40 mode( LMF = 4X16X4, each frame has 4 octets).  

Is it possible that Intel Jesd204B receiver uses two clocks to extract 8 octets frame to 2 4-octets frames. 

if not, what is the best option to transfer 16 ADCs( 16 bits resolution each ADC) through 4 Jesd204B lanes?

Appreciate your help, 

Sincerely,

David

 

 

 

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skbeh
Employee
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Hi David

I assume that if I set the TI AFE58JD48 to 80X mode( LMF = 4X16X8, each frame has 8 octets). set Intel IP core to X40 mode( LMF = 4X16X4, each frame has 4 octets). 

>> Is possible. The two reference designs below looks similar. 

In the Stratix 10 example design, the TI wideband ADC12DJ3200 device is the 12-bit converter which is capable of operating

at up to 3.2 giga samples per second (Gsps) in dual channel mode or 6.4 Gsps in an interleaved single channel mode. This design is programmed to run at the fastest sample rate of 6.4 Gsps in single channel mode, where this mode effectively interleaves the two analog-to-digital converter (ADC) channels together to form a single channel ADC at twice the sampling rate.


1) AN803: Implementing Synchronized ADC Multi-Link Design with JESD204B RX IP Core

https://www.intel.com/content/www/us/en/design-example/714466/arria-10-an803-implementing-synchronized-adc-multi-link-design-with-jesd204b-rx-ip-core.html


2) AN833: Intel® Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design

https://www.intel.com/content/www/us/en/docs/programmable/683049/current/gx-16-lane-rx-jesd204b-adc12dj3200-interoperability.html


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