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5954 Discussions

GMII interfaec for GigaE in LLE + Native PHY IP.

ASey
Beginner
1,033 Views

Hello guys,

 

I want to configure GigE using LLE IP and native PHY on cyclone 10gx EVB. Gmii_rx_d [8] on the MAC side is connected to rx_parallel_data [8] on native PHY. However, gmii_rx_dv [1] does not know which signal from PHY should be connected.

Usually, the IP is the gmii interface in PHY, but the native PHY does not

I do not know if I made the wrong setting.

Please ask for help if you know.

 

One mere thing is gmii_tx_en.

 

Thank you.

0 Kudos
2 Replies
ASey
Beginner
149 Views

In addition,

Development environment : Quartus 18.0 pro / LLE ip + Native PHY ip​ / qsys

​case : 10g interface [ parallel data & control ] <=>[gmii]

wire [7:0]                    xgmii_tx_control;

wire [63:0]                  xgmii_tx_data;

wire [71:0]     xgmii_tx;

 

wire [7:0]                    xgmii_rx_control;

wire [63:0]                  xgmii_rx_data;

wire [71:0]     xgmii_rx;

 

assign xgmii_tx_data = {

  xgmii_tx[70:63],

  xgmii_tx[61:54],

  xgmii_tx[52:45],

  xgmii_tx[43:36],

  xgmii_tx[34:27],

  xgmii_tx[25:18],

  xgmii_tx[16:9],

  xgmii_tx[7:0]

};

 

assign xgmii_tx_control = {

  xgmii_tx[71],

  xgmii_tx[62],

  xgmii_tx[53],

  xgmii_tx[44],

  xgmii_tx[35],

  xgmii_tx[26],

  xgmii_tx[17],

  xgmii_tx[8]

};

 

assign xgmii_rx = {

  xgmii_rx_control[7], xgmii_rx_data[63:56],

  xgmii_rx_control[6], xgmii_rx_data[55:48],

  xgmii_rx_control[5], xgmii_rx_data[47:40],

  xgmii_rx_control[4], xgmii_rx_data[39:32],

  xgmii_rx_control[3], xgmii_rx_data[31:24],

  xgmii_rx_control[2], xgmii_rx_data[23:16],

  xgmii_rx_control[1], xgmii_rx_data[15:8],

  xgmii_rx_control[0], xgmii_rx_data[7:0]};

if i had to make 1g.......​ when phy to mac (rx) , mac to phy (tx)

rx_gmii_d

rx_ gmii_dv

rx_gmii_err

 

tx_gmii_d

tx_gmii_en

tx_gmii_err

BoonT_Intel
Moderator
149 Views

Hi,

For C10 GX LLE with NativePHY design. I will suggest you refer to the example design that describe in this user guide.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20162.pdf

This design demonstrate ethernet solution using LL10GbE with native PHY IP.

 

Hope this helps.

 

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